Abstract: A signal buffer circuit includes a buffer to conduct a buffering operation for transmitting a signal to a subsequent unit; a resistor connected between an input side and an output side of the buffer; and a variable impedance device connected in series to the output side of the buffer. The variable impedance device is at low impedance when the buffer is conducting the buffering operation and at high impedance when the buffer is not conducting the buffering operation.

Abstract: The analog signal buffer is connected with a photoelectric converter to convert an optical image to an analog signal and an analog signal processing circuit to convert the analog signal to a digital signal, and transmits the analog signal to the analog signal processing circuit. The analog signal buffer includes a first buffer having a NPN transistor; and a second buffer having a PNP transistor. The first buffer includes a circuit to block a reverse current caused in the analog signal buffer by dropping of a voltage output from the photoelectric converter.

Abstract: There is provided a sensor driving circuit that includes: an image sensor that converts light reflected from an original to be read into electric signals; a driver circuit that drives the image sensor; and a timing generator circuit that outputs timing signals for use in control of the image sensor. The driver circuit includes a first inverting buffer circuit and a second inverting buffer circuit that are equivalent to each other and arranged in series connection of two stages with the first inverting buffer circuit at the first stage of the two stages. The timing signal output from the timing generator circuit has the same polarity as the polarity of an input signal fed to the image sensor.

Abstract: The photoelectric conversion device includes a photoelectric conversion element configured to convert light reflected from an original image to electrical signals and a clock generator configured to generate driving signals for driving the photoelectric conversion element from a reference clock. Each of the driving signals is generated using the same logic gate or substantially the same logic gate.

Abstract: The spread spectrum clock generator (SSCG) includes a phase comparator detecting phase difference between input clock and feedback clock; a charge pump supplying current depending on the phase difference; a loop filter converting the current to smoothed voltage; a voltage controlled oscillator generating a spread spectrum clock signal depending on the smoothed voltage; and a modulation signal generator generating modulation signal having amplitude depending on a modulation width set value. The SSCG further includes a modulation width detector detecting modulation width of the spread spectrum clock signal while comparing the modulation width with a modulation width target value to update the modulation width set value to narrow difference between the detected modulation width and the modulation width target value, followed by feeding back the updated modulation width set value to the modulation signal generator.

Abstract: Example embodiments of the present invention relate generally to a buffer circuit capable of suppressing the adverse influence of excessive voltage or current output from a photoelectric converting element on an analog signal processing circuit coupled to the photoelectric converting element, and an image reading apparatus or image forming apparatus incorporating the photoelectric converting element, the buffer circuit, and the analog signal processing circuit.

Abstract: A scanner, including a photoelectric conversion element photoelectrically converting light reflected from an original image to form an image signal; a timing generation circuit generating a drive signal for the photoelectric conversion element; a drive circuit driving the photoelectric conversion element; a signal processing circuit subjecting a sample hold signal fed in through the drive circuit and the image signal to an A/D conversion; and a control circuit turning on and off the sample hold signal when the scanner is powered on and off, respectively.

Abstract: An image reading device includes a charge-coupled device that generates and outputs an image signal, a timing generator that outputs a frequency-modulated clock, a modulation signal detector that detects a modulation signal being a signal corresponding to a change in frequency of the clock, an amplitude controller that controls an amplitude of the modulation signal, and a signal combining unit that superimposes the modulation signal after the amplitude is controlled on the image signal.

Abstract: A first clamping unit clamps a base voltage of an input image signal to a predetermined reference voltage. A sampling-and-holding unit samples and holds the image signal after clamping or a reference signal that becomes the base voltage of the image signal. An amplifying unit amplifies the image signal sampled and held by the sampling-and-holding unit. An analog-to-digital converting unit converts the image signal after amplification into a digital image signal. A second clamping unit clamps the reference signal to a predetermined voltage.

Abstract: Example embodiments of the present invention relate generally to a buffer circuit capable of suppressing the adverse influence of excessive voltage or current output from a photoelectric converting element on an analog signal processing circuit coupled to the photoelectric converting element, and an image reading apparatus or image forming apparatus incorporating the photoelectric converting element, the buffer circuit, and the analog signal processing circuit.