Abstract: A reset circuit includes an invertor having one control input terminal to which a positive supply voltage and a potential lower than GND are supplied, and an n-channel transistor having a gate terminal connected to an output terminal of the invertor, a source terminal connected to a potential lower than the GND and a drain terminal connected to the GND.

Abstract: To improve operation reliability of a charge and discharge control circuit and a chargeable power supply unit using it, and to improve the life of secondary cell. In the charge and discharge control circuit of the chargeable power supply unit, the circuit surely keeps control operation during voltage of the cell falls down because of discharge current and, over-current state and over-discharge state occur at the same time.

Abstract: A plurality of combinations of overcurrent detection voltages and delay times are set in a charge and discharge control circuit. Accordingly, a charge and discharge control circuit is formed in which an overcurrent condition having unexpectedly large consumption current, such as a short circuit, does not damage the circuit.

Abstract: To obtain a required delay time at each control using one capacitor in common, a charge and discharge control circuit includes an overcharge detecting circuit, an overdischarging circuit, and an overcurrent detecting circuit and carries out charge and discharge control of a secondary cell by ON/OFF control. A delay circuit includes plural current sources or a resistor and a single capacitor to obtain a varying delay time in response to a signal from outside. The charge and discharge control circuit operates the delay circuit so that a required delay output is obtained from the delay circuit by a first control circuit and ON/OFF controls a switch circuit by a second control circuit so that a required charge and discharge control is carried out with delay by the delay output.

Abstract: There is provided a semiconductor device for a reference voltage which has flat temperature characteristics and which generates a low reference voltage. A depression type MOS transistor 101 and an enhancement type MOS transistor 102 are each connected in series. A high voltage supply terminal 103 is provided at the drain of the depression type MOS transistor. A low voltage supply terminal 104 is provided at the source of the enhancement type MOS transistors. The gate of the depression type MOS transistor is connected to the low voltage supply terminal 104. The gate and drain of the enhancement type MOS transistor are connected. An output terminal 105 is provided at a point where both MOS transistors are connected. This provides flat temperature characteristics and allows the generation of a low reference voltage.

Abstract: To obtain an extremely small constant current with high accuracy, a constant current circuit comprises a first constant-current source for producing a first constant current, a second constant-current source connected to the first constant-current source for producing a second constant current having a different value from that of the first current, and an output terminal from which a third constant current equal to the difference between the first and second constant currents is output, such that the third constant current having an extremely small value may be produced without the use of a constant current source capable of producing an extremely small constant current value. The first and second constant current sources may be connected in series with the output terminal connected therebetween, or in parallel through a current mirror circuit. In addition, the constant current circuit can be provided in a timer circuit to produce a very long constant time signal with great stability.