Patents by Inventor Masanao Yokoyama

Masanao Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240089637
    Abstract: An imaging apparatus of the present disclosure includes: a pixel array including a plurality of light-receiving pixels including a first light-receiving pixel, a second light-receiving pixel, and a third light-receiving pixel, each generating a pixel signal in response to a received light amount, in which the first light-receiving pixel, the second light-receiving pixel, and the third light-receiving pixel are arranged in this order in a first direction; and a readout section including a first AD converter that performs AD conversion on the basis of each of the pixel signal generated by the first light-receiving pixel and the pixel signal generated by the third light-receiving pixel, and a second AD converter that performs AD conversion on the basis of the pixel signal generated by the second light-receiving pixel.
    Type: Application
    Filed: December 23, 2021
    Publication date: March 14, 2024
    Inventor: MASANAO YOKOYAMA
  • Publication number: 20240077944
    Abstract: An information processing device estimates an attitude of a hand of a user holding a controller with the hand. The information processing device has an acquisition unit, a determination unit, and an estimation unit. The acquisition unit acquires inertial information from an inertial sensor provided in the controller. The determination unit determines whether a specific portion of the hand of the user is detected in a captured image acquired by imaging of an imaging unit. The estimation unit estimates the attitude of the hand of the user on a basis of the captured image and the inertial information in a case where the specific portion is detected in the captured image.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Inventor: Masanao YOKOYAMA
  • Publication number: 20230411430
    Abstract: Provided is a solid-state imaging device that readily accommodates a design change of a pixel chip or a circuit chip. The solid-state imaging device according to the present technology includes a pixel chip including a pixel having a photoelectric conversion element, at least one circuit chip including a circuit configured to process a signal generated in the pixel, and a connecting substrate electrically connecting the pixel chip and the circuit chip, in which the pixel chip, the connecting substrate, and the circuit chip are stacked in this order. It is possible to provide a solid-state imaging device that readily accommodates a design change of a pixel chip or a circuit chip on the basis of the solid-state imaging device according to the present technology.
    Type: Application
    Filed: October 4, 2021
    Publication date: December 21, 2023
    Inventor: MASANAO YOKOYAMA
  • Patent number: 11842469
    Abstract: An apparatus includes at least one memory configured to store instructions, at least one processor in communication with the at least one memory and configured to execute the instructions to receive a photographing instruction, and an optical system configured to perform a first photographing method before reception of the photographing instruction, and a second photographing method after reception of the photographing instruction. The at least one processor further executes instructions to combine a plurality of first images at different in-focus positions captured by using the first photographing method with a plurality of second images at different in-focus positions captured by using the second photographing method. The optical system performs readout an image sensor, while keeping the drive of a focus lens, in the first photographing method, and stops the focus lens at different positions in the second photographing method.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: December 12, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Saori Hoda, Masanao Yokoyama, Masahiro Yamashita, Hiroshi Yamazaki
  • Publication number: 20230328394
    Abstract: An information processing apparatus that displays a captured image captured by an imaging apparatus on a display unit, the information processing apparatus includes a display controller configured to perform display control to display an image of a region of interest included in the captured image, on the display unit, wherein, the display controller displays, in a case where the region of interest is in an angle of view of a frame of the captured image, the image of the region of interest included in the frame, and displays, in a case where the region of interest is off from the angle of view of the frame of the captured image, the image of the region of interest included in a preceding frame preceding the frame.
    Type: Application
    Filed: April 5, 2023
    Publication date: October 12, 2023
    Inventor: MASANAO YOKOYAMA
  • Publication number: 20210306550
    Abstract: An apparatus includes at least one memory configured to store instructions, at least one processor in communication with the at least one memory and configured to execute the instructions to receive a photographing instruction, and an optical system configured to perform a first photographing method before reception of the photographing instruction, and a second photographing method after reception of the photographing instruction. The at least one processor further executes instructions to combine a plurality of first images at different in-focus positions captured by using the first photographing method with a plurality of second images at different in-focus positions captured by using the second photographing method. The optical system performs readout an image sensor, while keeping the drive of a focus lens, in the first photographing method, and stops the focus lens at different positions in the second photographing method.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 30, 2021
    Inventors: Saori Hoda, Masanao Yokoyama, Masahiro Yamashita, Hiroshi Yamazaki
  • Patent number: 10611429
    Abstract: A motorcycle (300) includes a clutch lever (14), a clutch switch (15) configured to detect whether or not the clutch lever (14) is gripped, a vehicle speed sensor (16) configured to detect a vehicle speed, a hydraulic rear brake (18), a pressurizing unit (17) configured to perform a pressurizing process that applies an oil pressure to the rear brake (18), and a microcontroller (19) configured to control the pressurizing process by the pressurizing unit (17) based on results of the detection by the vehicle speed sensor (16) and the clutch switch (15).
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: April 7, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Shoji Nakashima, Masanao Yokoyama
  • Publication number: 20170267245
    Abstract: A motorcycle (300) includes a clutch lever (14), a clutch switch (15) configured to detect whether or not the clutch lever (14) is gripped, a vehicle speed sensor (16) configured to detect a vehicle speed, a hydraulic rear brake (18), a pressurizing unit (17) configured to perform a pressurizing process that applies an oil pressure to the rear brake (18), and a microcontroller (19) configured to control the pressurizing process by the pressurizing unit (17) based on results of the detection by the vehicle speed sensor (16) and the clutch switch (15).
    Type: Application
    Filed: January 4, 2017
    Publication date: September 21, 2017
    Inventors: Shoji NAKASHIMA, Masanao YOKOYAMA
  • Publication number: 20170270876
    Abstract: An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.
    Type: Application
    Filed: June 7, 2017
    Publication date: September 21, 2017
    Inventors: Masanao YOKOYAMA, Noboru OKUZONO
  • Patent number: 9711097
    Abstract: An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: July 18, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masanao Yokoyama, Noboru Okuzono
  • Patent number: 9208569
    Abstract: An image processing apparatus comprises a captured image data acquisition unit configured to acquire captured image data, an information acquisition unit configured to acquire information of object distances of objects, a refocus image generation unit configured to generate a refocus image at a predetermined focus position in the captured image data, a display unit configured to display the refocus image on a display medium, a designation unit configured to designate an address in the refocus image displayed by the display unit, and a distance calculation unit configured to calculate distances between the designated address and positions of the objects in the refocus image, wherein the refocus image generation unit generates a refocus image using, as a focus position, an object distance of one of the objects based on the distances.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 8, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masanao Yokoyama
  • Publication number: 20150154924
    Abstract: An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.
    Type: Application
    Filed: February 9, 2015
    Publication date: June 4, 2015
    Inventors: Masanao YOKOYAMA, Noboru OKUZONO
  • Patent number: 8988124
    Abstract: An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yokoyama, Noboru Okuzono
  • Publication number: 20140219576
    Abstract: An image processing apparatus comprises a captured image data acquisition unit configured to acquire captured image data, an information acquisition unit configured to acquire information of object distances of objects, a refocus image generation unit configured to generate a refocus image at a predetermined focus position in the captured image data, a display unit configured to display the refocus image on a display medium, a designation unit configured to designate an address in the refocus image displayed by the display unit, and a distance calculation unit configured to calculate distances between the designated address and positions of the objects in the refocus image, wherein the refocus image generation unit generates a refocus image using, as a focus position, an object distance of one of the objects based on the distances.
    Type: Application
    Filed: January 24, 2014
    Publication date: August 7, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Masanao Yokoyama
  • Publication number: 20120133407
    Abstract: An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 31, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Masanao YOKOYAMA, Noboru OKUZONO
  • Publication number: 20040201083
    Abstract: A hard-macro arranged on a semiconductor chip for constituting a part of a semiconductor integrated circuit includes at least one wire passing therethrough. The wire is formed in the hard-macro before the hard-macro is arranged on the semiconductor chip, and the wire starts a first outer edge of the hard-macro and terminates at a second outer edge of the hard-macro intersecting with the first outer edge.
    Type: Application
    Filed: April 9, 2004
    Publication date: October 14, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masanao Yokoyama
  • Patent number: D631438
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: January 25, 2011
    Assignee: Seiko Clock Inc.
    Inventors: Masanao Yokoyama, Satoru Yamauchi
  • Patent number: D680135
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: April 16, 2013
    Assignee: Seiko Clock Inc.
    Inventors: Satoru Yamauchi, Masanao Yokoyama