Patents by Inventor Masanari Takeyasu

Masanari Takeyasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Information delivering system
    Publication number: 20030114199
    Abstract: An information delivering system in which, when persons happen to see attractive information, access information, such as a phone number, a URL, an e-mail address, for getting access to further information relative to the contents of this attractive information can be easily taken into a portable information terminal. The information delivering system includes at least one information display medium; at least one information delivering unit which includes at least one transmitting side storing device; and a portable information terminal.
    Type: Application
    Filed: September 10, 2002
    Publication date: June 19, 2003
    Inventor: Masanari Takeyasu
  • Storage circuitry using sense amplifier shared between memories of differing number of rows
    Patent number: 5986913
    Abstract: A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a read/write operation, or to wait until a calculation is completed.
    Type: Grant
    Filed: April 14, 1994
    Date of Patent: November 16, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Jimmie Don Childers, Seiichi Yamamoto, Masanari Takeyasu
  • Storage circuit
    Patent number: 5671187
    Abstract: A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a readrite operation, or to wait until a calculation is completed.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 23, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Jimmie Don Childers, Seiichi Yamamoto, Masanari Takeyasu
  • Storage circuitry using sense amplifier shared between memories of differing number of rows
    Patent number: 5579273
    Abstract: A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a read/write operation, or to wait until a calculation is completed.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 26, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Jimmie D. Childers, Seiichi Yamamoto, Masanari Takeyasu
  • Storage circuitry using sense amplifier with temporary pause for voltage supply isolation
    Patent number: 5426610
    Abstract: A processor (10) comprises a plurality of processing elements each having an input register (11), first memory bank (12), first sense amplifier (40), ALU (13), output register (16), second memory bank (15) and second sense amplifier (42). The first sense amplifier (40) is shared between the input register (11) and first memory bank (12). The second sense amplifier (42) is shared between the output register (16) and second memory bank (15). The sense amplifier (40,42) may be paused to prevent voltage spikes during a read/write operation, or to wait until a calculation is completed.
    Type: Grant
    Filed: July 21, 1992
    Date of Patent: June 20, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Jimmie D. Childers, Seiichi Yamamoto, Masanari Takeyasu
  • Three transistor dual port dynamic random access memory gain cell
    Patent number: 5105387
    Abstract: The present invention relates generally to single instruction, multiple data processors. More particularly, the invention relates to processors having a one dimensional array of processing elements, that finds particular application in digital signal processing such as Improved Definition Television (IDTV). Additionally, the invention relates to improvements to the processors, television and video systems and other systems improvements and methods of their operation and control.
    Type: Grant
    Filed: October 13, 1989
    Date of Patent: April 14, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Jimmie D. Childers, Seiichi Yamamoto, Masanari Takeyasu