Abstract: An information processing device provided with: an information processor; a unit for detecting a reset of the information processor; an acquisition unit for acquiring log information from the information processor; at least two buffers for storing the log information acquired by the acquisition means; and a controller for switching the storage destination of the log information acquired by the acquisition means between the at least two buffers, before or after the reset is detected, when a condition has been satisfied in which a predetermined minimum amount or more of log information is not acquired.

Abstract: A control apparatus connectable to a plurality of electronic units via a bus, the control apparatus controlling operations of the plurality of electronic units, the control apparatus includes a first storage section for storing an operating information used for operating each of the plurality of electronic units, a second storage section for storing an identifying information used for identifying each of the electronic units, a controller for controlling to receive a start notification of one of the electronic units, query the one of the electronic units about the identifying information, receive the identifying information from the one of the electronic units, compare the received identifying information with the stored identifying information in the second storage section, and query the one of the electronic units about an operating information when the received identifying information is different from the stored identifying information.

Abstract: In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.

Abstract: In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.