Patents by Inventor Masanobu Iwasaki

Masanobu Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11941251
    Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: March 26, 2024
    Assignee: Kioxia Corporation
    Inventors: Yoshihisa Kojima, Masanobu Shirakawa, Kiyotaka Iwasaki
  • Patent number: 7465216
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: December 16, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Patent number: 7465221
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: December 16, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Publication number: 20070270086
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Application
    Filed: July 20, 2007
    Publication date: November 22, 2007
    Applicant: RENESAS TECHNOLOGY CORP
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Publication number: 20070264908
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Application
    Filed: July 20, 2007
    Publication date: November 15, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Patent number: 7258598
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: August 21, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Patent number: 6727170
    Abstract: There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: April 27, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yoshifumi Takata, Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki
  • Patent number: 6602725
    Abstract: The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: August 5, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki, Kakutaro Suda
  • Patent number: 6568996
    Abstract: The object of the present invention is to provide a polishing agent for processing semiconductor, which can control coagulation and sedimentation and has stable and re-productive polishing properties under a proper dispersing condition to prevent generation of polishing flaw. The polishing agent for processing semiconductor comprises a compound having glucose structure, polishing particles and water.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: May 27, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshio Kobayashi, Toshiyuki Toyoshima, Suguru Nagae, Masanobu Iwasaki, Kouichirou Tsutahara, Shin Hasegawa
  • Publication number: 20020065022
    Abstract: A first supply unit sprays and supplies abrasive slurry containing abrasive grains into a mixing unit. A second supply unit sprays and supplies additive into the mixing unit. A third supply unit sprays and supplies pure water into the mixing unit. The mixing unit mixes the mist of abrasive slurry, the mist of additive and the mist of pure water to prepare polishing solution, and supplies the polishing solution onto the major surface of a polishing stage.
    Type: Application
    Filed: August 23, 2001
    Publication date: May 30, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masanobu Iwasaki, Yoshio Hayashide
  • Publication number: 20020039875
    Abstract: The object of the present invention is to provide a polishing agent for processing semiconductor, which can control coagulation and sedimentation and has stable and re-productive polishing properties under a proper dispersing condition to prevent generation of polishing flaw. The polishing agent for processing semiconductor comprises a compound having glucose structure, polishing particles and water.
    Type: Application
    Filed: April 19, 2001
    Publication date: April 4, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Toshio Kobayashi, Toshiyuki Toyoshima, Suguru Nagae, Masanobu Iwasaki, Kouichirou Tsutahara, Shin Hasegawa
  • Publication number: 20020014682
    Abstract: The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.
    Type: Application
    Filed: September 26, 2001
    Publication date: February 7, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki, Kakutaro Suda
  • Publication number: 20010050440
    Abstract: There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device.
    Type: Application
    Filed: July 13, 2001
    Publication date: December 13, 2001
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yoshifumi Takata, Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki
  • Patent number: 6303944
    Abstract: The semiconductor device includes a semiconductor wafer which is partitioned into chip regions by scribe line area. A device pattern is formed in the device forming region included in the chip region. A monitor pattern is formed from the same material as that of the device patterns in the chip region simultaneously with the device pattern. An interlayer insulating film is formed in the chip region so as to cover the device pattern and the monitor pattern. The monitor pattern is used to measure the thickness of the interlayer insulating film.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: October 16, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki, Kakutaro Suda
  • Patent number: 6278187
    Abstract: There is described a semiconductor device which prevents a short circuit between a wiring layer formed in interlayer insulating films and vertical conductor plugs formed in the vicinity of the wiring layer, and a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: August 21, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshifumi Takata, Yuichi Sakai, Hiroyuki Chibahara, Masanobu Iwasaki
  • Patent number: 6211070
    Abstract: On a surface of a semiconductor substrate within a device forming region, a MOS transistor including a gate electrode, gate oxide film and source•drain is formed. An insulating layer is formed on the surface of the semiconductor substrate. In an opening of the insulating layer above the source•drain, a tungsten plug is formed. At a dicing line portion, the insulating layer has a trench portion. The trench portion is formed to surround the device forming region. A tungsten street having a top surface continuous to the top surface of the insulating layer is formed in the trench. By this semiconductor device, short-circuit between bonding pads and the like can be prevented, and the reliability can be improved.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: April 3, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masanobu Iwasaki, Katsuhiro Tsukamoto
  • Patent number: 5945716
    Abstract: On a surface of a semiconductor substrate within a device forming region, a MOS transistor including a gate electrode, gate oxide film and source.cndot.drain is formed. An insulating layer is formed on the surface of the semiconductor substrate. In an opening of the insulating layer above the source.cndot.drain, a tungsten plug is formed. At a dicing line portion, the insulating layer has a trench portion. The trench portion is formed to surround the device forming region. A tungsten street having a top surface continuous to the top surface of the insulating layer is formed in the trench. By this semiconductor device, short-circuit between bonding pads and the like can be prevented, and the reliability can be improved.
    Type: Grant
    Filed: November 3, 1992
    Date of Patent: August 31, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masanobu Iwasaki, Katsuhiro Tsukamoto
  • Patent number: 5470799
    Abstract: The present invention provides a method for removing a natural gas film or contaminant adhering on a surface of a silicon semiconductor substrate. The semiconductor substrate having the natural oxide film or contaminant adhered thereon is placed in a chamber. Then, a HCl gas is introduced into the chamber. The semiconductor substrate is heated at a temperature in the range of 200.degree..about.700.degree. C., while ultraviolet rays are irradiated into the chamber. According to the method, the reaction of the natural oxide with HCl gas is promoted by a synergistic effect of light and heat energy. Therefore, the natural oxide film or contaminant can be removed at a lower temperature with the help of the light energy.
    Type: Grant
    Filed: April 24, 1989
    Date of Patent: November 28, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiromi Itoh, Masanobu Iwasaki, Akira Tokui, Katsuhiro Tsukamoto
  • Patent number: 5429991
    Abstract: A method of forming a thin film for a semiconductor device, for forming a metal thin film by chemical vapor deposition on an intermediate layer which is provided on a substrate, comprises the steps of activating the surface of the intermediate layer by introducing a halide gas of a metal for forming the thin film onto the surface of the intermediate layer, forming nuclei on the surface of the intermediate layer by introducing a silane-system gas onto the activated surface of the intermediate layer, and introducing the halide gas and a reducing gas onto the surface of the intermediate layer formed with the nuclei, thereby depositing the metal thin film on the surface of the intermediate layer.
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: July 4, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masanobu Iwasaki, Hiromi Itoh
  • Patent number: 5407867
    Abstract: A method of and an apparatus for removing a naturally grown oxide film and contaminants on the surface of a semiconductor substrate and then forming a thin film on the cleaned surface. The semiconductor substrate is placed in a pretreatment chamber and then hydrogen chloride gas is introduced into the chamber. Then, the semiconductor substrate is heated at a temperature between 200.degree..about.700.degree. C. and the surface of the semiconductor substrate is irradiated with ultraviolet rays, whereby the naturally grown oxide film and other contaminants on the semiconductor substrate can be removed. Then, a thin film is formed on the cleaned surface of the semiconductor substrate by a CVD method or a sputter method. According to this method, the naturally oxide film and other contaminants can be removed from the surface of the semiconductor substrate at a low temperature and the thin film can be formed on the cleaned surface.
    Type: Grant
    Filed: September 22, 1992
    Date of Patent: April 18, 1995
    Assignee: Mitsubishki Denki Kabushiki Kaisha
    Inventors: Masanobu Iwasaki, Hiromi Itoh, Akira Tokui, Katsuyoshi Mitsui, Katsuhiro Tsukamoto