Patents by Inventor Masanobu Kitada
Masanobu Kitada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10734948Abstract: A crystal unit includes a package, a crystal element, and a temperature sensor. The crystal element includes a crystal blank and a pair of excitation electrodes on a pair of major surfaces of the crystal blank and is air-tightly sealed in the package. The temperature sensor is mounted in the package. The crystal blank includes a crystal plane inclined relative to the major surfaces in at least a portion of the side surfaces.Type: GrantFiled: October 1, 2018Date of Patent: August 4, 2020Assignee: KYOCERA CorporationInventor: Masanobu Kitada
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Publication number: 20190103836Abstract: A crystal unit includes a package, a crystal element, and a temperature sensor. The crystal element includes a crystal blank and a pair of excitation electrodes on a pair of major surfaces of the crystal blank and is air-tightly sealed in the package. The temperature sensor is mounted in the package. The crystal blank includes a crystal plane inclined relative to the major surfaces in at least a portion of the side surfaces.Type: ApplicationFiled: October 1, 2018Publication date: April 4, 2019Applicant: KYOCERA CorporationInventor: Masanobu KITADA
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Patent number: 10065395Abstract: A composite substrate comprising a monocrystalline support substrate made of an insulating material and a monocrystalline semiconductor part disposed as a layer on the upper surface of the support substrate. An interface region having a thickness of 5 nm from the bonding interface between the support substrate and the semiconductor part towards the semiconductor part side includes a metal comprising: a metal element excluding the materials constituting the main components of the support substrate and the semiconductor part; and an inert element selected from the group consisting of Ar, Ne, Xe, and Kr. The number of atoms per unit area of the inert element is greater than that of the metal and smaller than that of the element constituting the semiconductor part.Type: GrantFiled: May 29, 2014Date of Patent: September 4, 2018Assignee: KYOCERA CORPORATIONInventors: Hideki Matsushita, Masanobu Kitada, Tetsuhiro Osaki
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Patent number: 9837374Abstract: Provided is a device in which the metal content existing in a joining interface is controlled. A manufacturing method for the device comprises: a step in which the surfaces of a first substrate and a second substrate are activated using a FAB gun; a step in which a plurality of metals are discharged by using the FAB gun to sputter a discharged metal body comprising the plurality of metals, and the plurality of metals are affixed to the surfaces of the first substrate and the second substrate; a step in which the first substrate and the second substrate are joined at room temperature; and a step in which heating is performed at a temperature that is high in comparison to the agglomeration start temperature of the plurality of metals and of the elements that constitute the first substrate or the second substrate.Type: GrantFiled: September 9, 2013Date of Patent: December 5, 2017Assignee: KYOCERA CORPORATIONInventors: Hideki Matsushita, Masanobu Kitada
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Patent number: 9754815Abstract: A composite substrate 1 according to the present invention comprises: a supporting substrate 10 that is formed of an insulating material; a semiconductor part 20 that is disposed over the supporting substrate 10; and interfacial inclusions 30 that are present at the interface between the supporting substrate 10 and the semiconductor part 20 and contains Ni and Fe so that the ratio of Ni to Fe is 0.4 or more. Consequently, the present invention is able to provide a highly reliable composite substrate wherein the interfacial inclusions 30 are prevented from diffusing into the semiconductor part 20.Type: GrantFiled: September 29, 2014Date of Patent: September 5, 2017Assignee: KYOCERA CORPORATIONInventors: Hideki Matsushita, Masanobu Kitada
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Composite substrate with a high-performance semiconductor layer and method of manufacturing the same
Patent number: 9711418Abstract: Provided is a composite substrate which has a high-performance semiconductor layer. A composite substrate of the present invention comprises: a supporting substrate which is formed of an insulating material; a semiconductor layer which is formed of a single crystal semiconductor that is superposed on and joined to the supporting substrate; and interfacial inclusions which are present in the interface between the supporting substrate and the semiconductor layer at a density of 1012 atoms/cm2 or less, and which are formed of a metal element that is different from the constituent elements of the supporting substrate and the semiconductor layer.Type: GrantFiled: September 9, 2013Date of Patent: July 18, 2017Assignee: KYOCERA CORPORATIONInventors: Masanobu Kitada, Hideki Matsushita -
Patent number: 9496279Abstract: Provided is a composite substrate having a semiconductor layer wherein diffusion of a metal is suppressed. This composite substrate has: a single crystal supporting substrate composed of an insulating oxide; a semiconductor layer, which has one main surface overlapping the supporting substrate, and which is composed of a single crystal; and a polycrystalline or amorphous intermediate layer, which is positioned between the supporting substrate and the semiconductor layer, and which has, as a main component, an element constituting the supporting substrate or an element constituting the semiconductor layer, and in which the ratio of accessory components other than the main component is less than 1 mass %.Type: GrantFiled: February 28, 2013Date of Patent: November 15, 2016Assignee: Kyocera CorporationInventor: Masanobu Kitada
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Publication number: 20160247712Abstract: A composite substrate 1 according to the present invention comprises: a supporting substrate 10 that is formed of an insulating material; a semiconductor part 20 that is disposed over the supporting substrate 10; and interfacial inclusions 30 that are present at the interface between the supporting substrate 10 and the semiconductor part 20 and contains Ni and Fe so that the ratio of Ni to Fe is 0.4 or more. Consequently, the present invention is able to provide a highly reliable composite substrate wherein the interfacial inclusions 30 are prevented from diffusing into the semiconductor part 20.Type: ApplicationFiled: September 29, 2014Publication date: August 25, 2016Inventors: Hideki MATSUSHITA, Masanobu KITADA
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Publication number: 20160101598Abstract: A composite substrate comprising a monocrystalline support substrate made of an insulating material and a monocrystalline semiconductor part disposed as a layer on the upper surface of the support substrate. An interface region having a thickness of 5 nm from the bonding interface between the support substrate and the semiconductor part towards the semiconductor part side includes a metal comprising: a metal element excluding the materials constituting the main components of the support substrate and the semiconductor part; and an inert element selected from the group consisting of Ar, Ne, Xe, and Kr[[Xr]]. The number of atoms per unit area of the inert element is greater than that of the metal and smaller than that of the element constituting the semiconductor part.Type: ApplicationFiled: May 29, 2014Publication date: April 14, 2016Inventors: Hideki MATSUSHITA, Masanobu KITADA, Tetsuhiro OSAKI
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Patent number: 9287353Abstract: A composite substrate which includes a silicon layer having less lattice defects is provided. A composite substrate includes an insulating substrate and a functional layer of which one main surface is bonded to an upper surface of the substrate. A dopant concentration of the functional layer decreases from the other main surface toward the substrate side in a thickness direction of the functional layer.Type: GrantFiled: October 17, 2013Date of Patent: March 15, 2016Assignee: Kyocera CorporationInventors: Masanobu Kitada, Motokazu Ogawa, Yoshiyuki Kawaguchi
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Patent number: 9287351Abstract: [Problem] To provide a composite substrate which includes a silicon substrate having few lattice defects. [Solution] A composite substrate (50) that comprises a first substrate (10), which is constituted of a semiconductor material, a second substrate (40), which is constituted of an insulating material, and an oxide layer (30) and a semiconducting epitaxial layer (20) which have been disposed between the substrates (10) and (40) in this order from the second substrate (40) side, the oxide layer (30) having oxygen atoms arranged on the side thereof which faces the epitaxial layer (20).Type: GrantFiled: June 26, 2012Date of Patent: March 15, 2016Assignee: Kyocera CorporationInventors: Masanobu Kitada, Tomofumi Honjo
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Patent number: 9245942Abstract: A composite substrate having silicon substrate with excellent crystallinity and a method of manufacturing the composite substrate and an electronic component using the composite substrate are provided. A composite substrate (1) is configured to bond a support substrate (10) having electrical insulating property, and a silicon substrate (20) which is overlaid on the support substrate (10). The semiconductor substrate (20) of the composite substrate (1) includes a plurality of first regions (20x) in which a device function unit functioning as a semiconductor device is formed, and a second region (20y) located between these first regions (20x). In the semiconductor substrate (20) of the composite substrate (1), an amorphous form (22) containing silicon and a metal is present in the second region (20y).Type: GrantFiled: February 27, 2012Date of Patent: January 26, 2016Assignee: KYOCERA CORPORATIONInventor: Masanobu Kitada
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Publication number: 20150255354Abstract: Provided is a composite substrate which has a high-performance semiconductor layer. A composite substrate of the present invention comprises: a supporting substrate which is formed of an insulating material; a semiconductor layer which is formed of a single crystal semiconductor that is superposed on and joined to the supporting substrate; and interfacial inclusions which are present in the interface between the supporting substrate and the semiconductor layer at a density of 1012 atoms/cm2 or less, and which are formed of a metal element that is different from the constituent elements of the supporting substrate and the semiconductor layer.Type: ApplicationFiled: September 9, 2013Publication date: September 10, 2015Applicant: KYOCERA CorporationInventors: Masanobu Kitada, Hideki Matsushita
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Publication number: 20150206853Abstract: Provided is a device in which the metal content existing in a joining interface is controlled. A manufacturing method for the device comprises: a step in which the surfaces of a first substrate and a second substrate are activated using a FAB gun; a step in which a plurality of metals are discharged by using the FAB gun to sputter a discharged metal body comprising the plurality of metals, and the plurality of metals are affixed to the surfaces of the first substrate and the second substrate; a step in which the first substrate and the second substrate are joined at room temperature; and a step in which heating is performed at a temperature that is high in comparison to the agglomeration start temperature of the plurality of metals and of the elements that constitute the first substrate or the second substrate.Type: ApplicationFiled: September 9, 2013Publication date: July 23, 2015Applicant: KYOCERA CorporationInventors: Hideki Matsushita, Masanobu Kitada
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Publication number: 20150155299Abstract: Provided is a composite substrate having a semiconductor layer wherein diffusion of a metal is suppressed. This composite substrate has: a single crystal supporting substrate composed of an insulating oxide; a semiconductor layer, which has one main surface overlapping the supporting substrate, and which is composed of a single crystal; and a polycrystalline or amorphous intermediate layer, which is positioned between the supporting substrate and the semiconductor layer, and which has, as a main component, an element constituting the supporting substrate or an element constituting the semiconductor layer, and in which the ratio of accessory components other than the main component is less than 1 mass %.Type: ApplicationFiled: February 28, 2013Publication date: June 4, 2015Inventor: Masanobu Kitada
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Publication number: 20140167230Abstract: [Problem] To provide a composite substrate which includes a silicon substrate having few lattice defects. [Solution] A composite substrate (50) that comprises a first substrate (10), which is constituted of a semiconductor material, a second substrate (40), which is constituted of an insulating material, and an oxide layer (30) and a semiconducting epitaxial layer (20) which have been disposed between the substrates (10) and (40) in this order from the second substrate (40) side, the oxide layer (30) having oxygen atoms arranged on the side thereof which faces the epitaxial layer (20).Type: ApplicationFiled: June 26, 2012Publication date: June 19, 2014Applicant: KYOCERA CORPORATIONInventors: Masanobu Kitada, Tomofumi Honjo
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Publication number: 20140042598Abstract: A composite substrate which includes a silicon layer having less lattice defects is provided. A composite substrate includes an insulating substrate and a functional layer of which one main surface is bonded to an upper surface of the substrate. A dopant concentration of the functional layer decreases from the other main surface toward the substrate side in a thickness direction of the functional layer.Type: ApplicationFiled: October 17, 2013Publication date: February 13, 2014Applicant: Kyocera CorporationInventors: Masanobu KITADA, Motokazu Ogawa, Yoshiyuki Kawaguchi
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Publication number: 20130328048Abstract: A composite substrate having silicon substrate with excellent crystallinity and a method of manufacturing the composite substrate and an electronic component using the composite substrate are provided. A composite substrate (1) is configured to bond a support substrate (10) having electrical insulating property, and a silicon substrate (20) which is overlaid on the support substrate (10). The semiconductor substrate (20) of the composite substrate (1) includes a plurality of first regions (20x) in which a device function unit functioning as a semiconductor device is formed, and a second region (20y) located between these first regions (20x). In the semiconductor substrate (20) of the composite substrate (1), an amorphous form (22) containing silicon and a metal is present in the second region (20y).Type: ApplicationFiled: February 27, 2012Publication date: December 12, 2013Applicant: Kyocera CorporationInventor: Masanobu Kitada
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Publication number: 20130299954Abstract: A composite substrate which includes a silicon layer having less lattice defects is provided. A composite substrate includes an insulating substrate and a functional layer of which one main surface is bonded to an upper surface of the substrate. A dopant concentration of the functional layer decreases from the other main surface toward the substrate side in a thickness direction of the functional layer.Type: ApplicationFiled: November 30, 2011Publication date: November 14, 2013Applicant: Kyocera CorporationInventors: Masanobu Kitada, Motokazu Ogawa
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Publication number: 20130119519Abstract: Provided are a composite substrate which includes a silicon substrate having improved crystallinity, a method for manufacturing a composite substrate, and a method for manufacturing an electronic component. A composite substrate is formed by bonding a semiconductor substrate onto a support substrate having electric insulating properties. The semiconductor substrate is formed of silicon. The semiconductor substrate includes a plurality of first regions on each of which an element portion which functions as a semiconductor device is formed, and a second region which is positioned between the plurality of first regions. In the semiconductor substrate, an oxidized portion which is composed of silicon oxide is formed on a bottom surface of the second region.Type: ApplicationFiled: July 29, 2011Publication date: May 16, 2013Applicant: KYOCERA CORPORATIONInventor: Masanobu Kitada