Abstract: A simulator capable of counting a number of events occurring in each of functional modules constituting an LSI and calculating an index value for selecting a simulation method for each functional module in simulation of an operation of the LSI with a first test vector set. The simulator further capable of selecting one simulation method among a plurality of simulation methods for each functional module based on the selection index value, and of controlling execution of simulation of the LSI operation with a second test vector set in the simulation method selected for each functional module.

Abstract: A simulation executing unit includes a conversion unit and a simulation portion. The conversion unit includes a circuit dividing portion, a circuit converting portion and a converted logic circuit generating portion, and the circuit dividing portion divides a logic circuit into combinational partial circuits each interposed between registers or between a register and an input pin or the like. The circuit converting portion generates, on the basis of the divided combinational partial circuits, a converted logic circuit by modifying allocation of registers included in the logic circuit, so as to decrease the number of registers included in the logic circuit without changing the output timing of the logic circuit. The simulation unit performs a simulation on the converted logic circuit.

Abstract: Test vector storing means outputs data for simulation at a predetermined transfer speed. A signal processor executes the simulation of a digital signal processing circuit by using the data for simulation and outputs the simulation result. Simulation result storing means stores the simulation result input at a predetermined transfer speed. Simulation program generating means generates a simulation program, in advance, which is executed by the signal processor and has throughput that is coincident with the output speed of data of the test vector storing means. Synchronizing means synchronizes the data transfer of the test vector storing means, the execution speed of the signal processor, and the data transfer of the simulation result storing means.