Abstract: A semiconductor light-emitting element includes: a semiconductor stack including an n-type layer and a p-type layer and having at least one n exposure portion being a recess where the n-type layer is exposed; a p wiring electrode layer on the p-type layer; an insulating layer (i) continuously covering inner lateral surfaces of at least one n exposure portion and part of a top surface of the p wiring electrode layer and (ii) having an opening portion that exposes the n-type layer; an n wiring electrode layer disposed above the p-type layer and the p wiring electrode layer and in contact with the n-type layer in the opening portion; and at least one first n connecting member connected to the n wiring electrode layer in at least one first n terminal region. The n wiring electrode layer and the p-type layer are disposed below at least one first n terminal region.

Abstract: A semiconductor light-emitting element includes: a semiconductor stack including an n-type, layer and a p-type layer and having at least one n exposure portion being a recess where the n-type layer is exposed; a p wiring electrode layer on the p-type layer; an insulating layer (i) continuously covering inner lateral surfaces of at least one n exposure portion and part of a top surface of the p wiring electrode layer and (ii) having an opening portion that exposes the n-type layer; an n wiring electrode layer disposed above the p-type layer and the p wiring electrode layer and in contact with the n-type layer in the opening portion; and at least one first n connecting member connected to the n wiring electrode layer in at least one first n terminal region. The n wiring electrode layer and the p-type layer are disposed below at least one first n terminal region.

Abstract: A semiconductor light-emitting element includes: a semiconductor stack including an n-type, layer and a p-type layer and haying at least one n exposure portion being a recess where the n-type layer is exposed; a p wiring electrode layer on the p-type layer; an insulating layer (i) continuously covering inner lateral surfaces of at least one n exposure portion and part of a top surface of the p wiring electrode layer and (ii) having an opening portion that exposes the n-type layer; an n wiring electrode layer disposed above the p-type layer and the p wiring electrode layer and in contact with the n-type layer in the opening portion; and at least one first n connecting member connected to the n wiring electrode layer in at least one first n terminal region. The n wiring electrode layer and the p-type layer are disposed below at least one first n terminal region.

Abstract: A hetero-junction bipolar transistor includes a sub-collector layer formed on a substrate and having conductivity, a first collector layer formed on the sub-collector layer and a second collector layer formed on the first collector layer and having the same conductive type as a conductive type of the sub-collector layer. In the first collector layer, a delta-doped layer is provided.

Abstract: A hetero-junction bipolar transistor includes a sub-collector layer formed on a substrate and having conductivity, a first collector layer formed on the sub-collector layer and a second collector layer formed on the first collector layer and having the same conductive type as a conductive type of the sub-collector layer. In the first collector layer, a delta-doped layer is provided.

Abstract: A hetero-junction bipolar transistor includes a sub-collector layer formed on a substrate and having conductivity, a first collector layer formed on the sub-collector layer and a second collector layer formed on the first collector layer and having the same conductive type as a conductive type of the sub-collector layer. In the first collector layer, a delta-doped layer is provided.

Abstract: A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collector 110 and is formed on the sub-collector layer 110; a second collector layer 132 that is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layer 110 and is formed on the first collector layer 121; a p-type base layer 133 that is made of GaAs and is formed on the second collector layer 132; and emitter layer 134 that is made of a semiconductor material with a larger band gap than that of the base layer 133 and is formed on the base layer 133.

Abstract: A semiconductor device is provided having an improved breakdown voltage on high power output, the semiconductor device comprising a n-type GaAs subcollector layer, a n-type GaAs intermediate collector layer formed between a collector layer and the subcollector layer, the n-type GaAs collector layer, a p-type GaAs base layer, a n-type InGaP second emitter layer, a n-type GaAs first emitter layer, and a n-type InGaAs emitter contact layer, and a concentration of impurities in the intermediate collector layer is higher than a concentration of impurities in the collector layer and is lower than a concentration of impurities in the subcollector layer.

Abstract: A semiconductor device includes a substrate with a via hole. An electrode is formed on a surface of the substrate so that a portion of the electrode extends through the via hole. A photosensitive resin is formed over the surface so as to cover an aperture of the via hole.

Abstract: A GaAs substrate 200 is rotated, a photosensitive silicone resist 260 is applied on a surface of the GaAs substrate 200 on which an aperture of a hole 310 to be a via hole, and an inside of the hole 310 to be the via hole is filled in with the photosensitive silicone resist 260. Next, the GaAs substrate 200 is further rotated, changing the number of revolutions (rpm), and the photosensitive silicone resist 260 on the GaAs substrate is flattened. Next, a reverse side of the GaAs substrate is grinded, the hole 310 to be the via hole penetrates the GaAs substrate 200 from the surface to the reverse side and the via hole 220 is formed. Next, a reverse side electrode 240 is formed on the reverse side of the GaAs substrate 200. Next, the GaAs sustrate 200 is divided chip by chip and chips are laid on a substrate for assembly 270 via an adhesive metal 280.

Abstract: A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collector 110 and is formed on the sub-collector layer 110; a second collector layer 132 that is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layer 110 and is formed on the first collector layer 121; a p-type base layer 133 that is made of GaAs and is formed on the second collector layer 132; and emitter layer 134 that is made of a semiconductor material with a larger band gap than that of the base layer 133 and is formed on the base layer 133.

Abstract: It is the object of the present invention to provide a semiconductor device having an improved breakdown voltage on high power output, the semiconductor device comprising a n-type GaAs subcollector layer 101, a n-type GaAs intermediate collector layer 102 formed between a collector layer 103 and the subcollector layer 101, the n-type GaAs collector layer 103, a p-type GaAs base layer 104, a n-type InGaP second emitter layer 105, a n-type GaAs first emitter layer 106, and a n-type InGaAs emitter contact layer 107, and a concentration of impurities in the intermediate collector layer 102 is higher than a concentration of impurities in the collector layer 103 and is lower than a concentration of impurities in the subcollector layer 101.

Abstract: A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collector 110 and is formed on the sub-collector layer 110; a second collector layer 132 that is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layer 110 and is formed on the first collector layer 121; a p-type base layer 133 that is made of GaAs and is formed on the second collector layer 132; and emitter layer 134 that is made of a semiconductor material with a larger band gap than that of the base layer 133 and is formed on the base layer 133.

Abstract: A GaAs substrate 200 is rotated, a photosensitive silicone resist 260 is applied on a surface of the GaAs substrate 200 on which an aperture of a hole 310 to be a via hole, and an inside of the hole 310 to be the via hole is filled in with the photosensitive silicone resist 260. Next, the GaAs substrate 200 is further rotated, changing the number of revolutions (rpm), and the photosensitive silicone resist 260 on the GaAs substrate is flattened. Next, a reverse side of the GaAs substrate is grinded, the hole 310 to be the via hole penetrates the GaAs substrate 200 from the surface to the reverse side and the via hole 220 is formed. Next, a reverse side electrode 240 is formed on the reverse side of the GaAs substrate 200. Next, the GaAs sustrate 200 is divided chip by chip and chips are laid on a substrate for assembly 270 via an adhesive metal 280.

Abstract: A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collector 110 and is formed on the sub-collector layer 110; a second collector layer 132 that is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layer 110 and is formed on the first collector layer 121; a p-type base layer 133 that is made of GaAs and is formed on the second collector layer 132; and emitter layer 134 that is made of a semiconductor material with a larger band gap than that of the base layer 133 and is formed on the base layer 133.

Abstract: A method of producing a hetero-junction bipolar transistor includes: laminating semiconductor layers that are to be a subcollector layer, a collector layer, a base layer, an emitter layer and an emitter cap layer successively on one surface of a semi-insulating substrate; and forming an electrode layer on the emitter cap layer. The method also includes adjusting the shape of the emitter cap layer to be a predetermined shape by wet etching; and removing end portions of the electrode layer so that the edges of the electrode layer are substantially aligned to the edges of the top face of the emitter cap layer. Furthermore, the method includes removing a surface oxidized layer formed on the emitter layer. Thus, defective etching of the emitter layer including an element P of group V is resolved, and a hetero-junction bipolar transistor having predetermined properties can be produced stably.

Abstract: A GaAs substrate 200 is rotated, a photosensitive silicone resist 260 is applied on a surface of the GaAs substrate 200 on which an aperture of a hole 310 to be a via hole, and an inside of the hole 310 to be the via hole is filled in with the photosensitive silicone resist 260. Next, the GaAs substrate 200 is further rotated, changing the number of revolutions (rpm), and the photosensitive silicone resist 260 on the GaAs substrate is flattened. Next, a reverse side of the GaAs substrate is grinded, the hole 310 to be the via hole penetrates the GaAs substrate 200 from the surface to the reverse side and the via hole 220 is formed. Next, a reverse side electrode 240 is formed on the reverse side of the GaAs substrate 200. Next, the GaAs sustrate 200 is divided chip by chip and chips are laid on a substrate for assembly 270 via an adhesive metal 280.

Abstract: A method of producing a hetero-junction bipolar transistor includes: laminating semiconductor layers that are to be a subcollector layer, a collector layer, a base layer, an emitter layer and an emitter cap layer successively on one surface of a semi-insulating substrate; and forming an electrode layer on the emitter cap layer. The method also includes adjusting the shape of the emitter cap layer to be a predetermined shape by wet etching; and removing end portions of the electrode layer so that the edges of the electrode layer are substantially aligned to the edges of the top face of the emitter cap layer. Furthermore, the method includes removing a surface oxidized layer formed on the emitter layer. Thus, defective etching of the emitter layer including an element P of group V is resolved, and a hetero-junction bipolar transistor having predetermined properties can be produced stably.

Abstract: A semiconductor device includes two or more semiconductor elements provided on a semi-insulating substrate with a buffer layer and an interlevel film being interposed therebetween, an element isolating portion provided as a result of forming a groove between the two or more semiconductor elements through the buffer layer and the interlevel film so as to reach the semi-insulating substrate, and a protective film for protecting at least ends of the buffer layer in the vicinity of the element isolating portion.