Patents by Inventor Masanobu Ogino
Masanobu Ogino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080242067Abstract: A semiconductor substrate is disclosed, which comprises a lightly doped substrate that contains impurities at a low concentration, a heavily doped diffusion layer which is formed over a top of the lightly doped substrate and is higher in impurity concentration than the lightly doped substrate, and an epitaxial layer which is formed over a top of the heavily doped diffusion layer and contains impurities at a lower concentration than the heavily doped diffusion layer.Type: ApplicationFiled: April 29, 2008Publication date: October 2, 2008Inventors: Masanobu OGINO, Yoshikatsu Suto, Yoshiro Baba
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Publication number: 20040124445Abstract: A semiconductor substrate is disclosed, which comprises a lightly doped substrate that contains impurities at a low concentration, a heavily doped diffusion layer which is formed over a top of the lightly doped substrate and is higher in impurity concentration than the lightly doped substrate, and an epitaxial layer which is formed over a top of the heavily doped diffusion layer and contains impurities at a lower concentration than the heavily doped diffusion layer.Type: ApplicationFiled: November 17, 2003Publication date: July 1, 2004Inventors: Masanobu Ogino, Yoshikatsu Suto, Yoshiro Baba
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Patent number: 5951755Abstract: A manufacturing method for manufacturing a semiconductor substrate has first annealing step for annealing silicon single crystal to permit oxygen embryos or oxygen precipitations grown from the oxygen embryos precipitating in a predetermined region and a second annealing step for permitting said oxygen embryos or said oxygen precipitations to contract using a second temperature range higher than the first temperature range, said second temperature range being high enough to contract said oxygen embryos and low enough to prevent redistribution of boron from affecting to device characteristics, to form a denuded zone in said predetermined region at the principal surface. An inspection method for inspecting a semiconductor substrate further has measuring step, subsequent to said first and second annealing steps for measuring the density of oxygen embryos grown into oxygen precipitations among those precipitated in said silicon single crystal.Type: GrantFiled: February 14, 1997Date of Patent: September 14, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Moriya Miyashita, Masanobu Ogino, Tadahide Hoshi, Masanori Numano, Shuichi Samata, Akiko Sekihara, Keiko Akita
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Patent number: 5945703Abstract: In a semiconductor memory device, a capacitor with a trench having a laterally expanded bottom part is provided, the area above the laterally expanded part being provided for a transistor and cell separation, this resulting in an increase in the degree of integration. This laterally expanded part is formed by etching a silicon oxide film which is sandwiched between a substrate and a silicon layer, and is obtained by forming a depression in a semiconductor substrate beforehand. A silicon layer or another semiconductor substrate is laminated by bonding to a semiconductor substrate such as this into which is formed a depression, a trench which extends to this depression being formed, and the required films being formed to obtain the desired trench capacitor. By forming an oxide film on all of or the depression part of the semiconductor substrate into which is formed the depression, it is possible to eliminate the influence of radiation, by improving insulation properties.Type: GrantFiled: December 7, 1994Date of Patent: August 31, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyoshi Furukawa, Masanobu Ogino, Koichi Kishi
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Patent number: 5213993Abstract: A manufacturing method of this invention improves nonuniformity in film thickness of a circuit element formation region produced due to a poor flatness of a semiconductor substrate in the manufacture of a semiconductor substrate having a dielectric isolating structure. Mirror-polished surfaces of first and second semiconductor substrates are opposed and bonded to each other so as to sandwich a dielectric having a predetermined thickness, and the first semiconductor substrate is ground from the surface opposite to the adhesion surface to have a predetermined thickness with reference to the dielectric. An impurity is doped in the first semiconductor substrate to form a high-concentration impurity layer having an impurity concentration corresponding to a predetermined low-concentration impurity layer having a predetermined thickness thereon, thereby constituting a circuit element region.Type: GrantFiled: March 6, 1992Date of Patent: May 25, 1993Assignee: Kabushiki Kaisha TobishaInventors: Masanobu Ogino, Tsutomu Amai, Takanobu Kamakura
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Patent number: 5188987Abstract: A method of manufacturing a semiconductor device comprises the steps of performimg selective vapor growth on a semiconductor substrate, and polishing a surface of an insulative film formed on said semiconductor substrate subsequent to the selective vapor growth step.Type: GrantFiled: June 12, 1991Date of Patent: February 23, 1993Assignee: Kabushiki Kaisha ToshibaInventor: Masanobu Ogino
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Patent number: 5132770Abstract: A semiconductor device includes a composite semiconductor substrate formed by disposing first and second semiconductor substrates in close contact with each other. At least one dielectric layer is formed in the composite semiconductor substrate. At least one polycrystalline layer is formed adjacent to the dielectric layer.Type: GrantFiled: January 10, 1991Date of Patent: July 21, 1992Assignee: Kabushiki Kaisha ToshibaInventor: Masanobu Ogino
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Patent number: 5096839Abstract: The ratio between variations in the oxygen concentration before and after a silicon wafer is subjected to two types of heat treatments in which the temperatures and processing times are different is defined. The silicon wafer is subjected to a first heat treatment, and the interstitial oxygen concentrations before and after the first heat treatment are respectively set to [Oi].sub.1ini and [Oi].sub.1af. The silicon wafer is successively subjected to second and third heat treatments, and the interstitial oxygen concentrations before and after the second and third heat treatments are respectively set to [Oi].sub.2ini and [Oi].sub.2af. At this time, the interstitial oxygen concentrations [Oi].sub.1ini, [Oi].sub.1af, [Oi].sub.2ini and [Oi].sub.2af are so set as to satisfy the condition that ([Oi].sub.2ini -[Oi].sub.2af)/[Oi].sub.1ini -[Oi].sub.1af).gtoreq.20.Type: GrantFiled: April 30, 1991Date of Patent: March 17, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Amai, Masanobu Ogino
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Patent number: 5023696Abstract: A semiconductor element is formed in a composite substrate constructed by fixing two semiconductor substrates in close contact with each other, and crystal defects are formed in that portion of at least one of the two semiconductor substrates which lies near the junction plane of the two semiconductor substrates. The crystal defects act as the center of the recombination of excess minority carriers accumulated in an active region of the semiconductor element.Type: GrantFiled: February 3, 1989Date of Patent: June 11, 1991Assignee: Kabushiki Kaisha ToshibaInventor: Masanobu Ogino
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Patent number: 4990459Abstract: A drop which is hydrophobic to the surface of an object to be measured is dropped on the surface of the object and moved so as to be brought into contact with the overall surface of the object to be measured. After the movement, the drop is recovered and analyzed by chemical analysis to measure the kind of element and content of an impurity adsorbed on the surface of the object to be measured.Type: GrantFiled: April 18, 1989Date of Patent: February 5, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Ayako Maeda, Mokuji Kageyama, Shintaro Yoshii, Masanobu Ogino
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Patent number: 4958373Abstract: A defect-recognition processing apparatus converts into a defect image pattern, via a television camera, crystal defects present on the surface of an object under inspection, to process an image signal, by means of an image processing device, which corresponds to the defect image pattern, to measure rectangular images in terms of their length and their ratio between L.sub.Y and L.sub.X (L.sub.Y : a length in a longitudinal direction and L.sub.X : a length in the lateral direction of the wafer) and to detect defects developed on the surface of the aforementioned object.Type: GrantFiled: March 29, 1988Date of Patent: September 18, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Toshiro Usami, Hiroyuki Kamijo, Takao Ohta, Masanobu Ogino
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Patent number: 4894206Abstract: The present invention discloses a crystal pulling apparatus having a double-crucible structure, wherein an inner crucible is located in an outer crucible. An end of a pipe-like passage is located in a through hole formed in a side wall of an inner crucible located in an outer crucible, and a melt is supplied from the outer crucible to the inner crucible through the pipe-like passage, during crystal pulling. During melting or neckdown, prior to crystal pulling, diffusion of an impurity between the melts in the outer crucible and the inner crucible, and exchange of the melts between the outer crucible and the inner crucible are prevented by the pipe-like passage.Type: GrantFiled: September 1, 1987Date of Patent: January 16, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Youji Yamashita, Masakatu Kojima, Yoshiaki Matsushita, Masanobu Ogino
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Patent number: 4721991Abstract: A semiconductor device having an electroconductive portion made of a multi-component alloy which may be represented by a formula:M.Fe.sub.x.Si.sub.ywherein 0<x<0.17, 2.ltoreq.y.ltoreq.3 and M is a metal or metals selected from Groups IV, V and VI elements in the Periodic Table.Type: GrantFiled: May 6, 1985Date of Patent: January 26, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Reiji Ohtaki, Masanobu Ogino, Yuuichi Mikata