Patents by Inventor Masanobu Shoji
Masanobu Shoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10017734Abstract: The present invention provides a method of more efficiently producing a high-quality dopaminergic neuron from neural progenitor cells, specifically, a production method of a dopaminergic neuron including a step of culturing neural progenitor cells in a medium containing (i) a cAMP analog and (ii) a MEK inhibitor. Moreover, the present invention also provides a medicament containing a dopaminergic neuron obtained by the method, and a reagent and a kit to be used for the method.Type: GrantFiled: August 6, 2014Date of Patent: July 10, 2018Assignee: TAKEDA PHARMACEUTICAL COMPANY LIMITEDInventor: Masanobu Shoji
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Publication number: 20170367195Abstract: The manufacturing method includes (a) preparing first printed circuit board and second printed circuit board, the first printed circuit board being provided with a plurality of first terminals, the second printed circuit board being provided with a plurality of second terminals, and the first terminals or the second terminals being coated with solders; and (b) connecting the first terminals and the second terminals, respectively, via respective solders by performing thermocompression on connecting portions of the first printed circuit board and the second printed circuit board. Each second terminal includes a first end portion and a second end portion in a long axis direction, and in the step (b), pressure is applied to each second terminal such that the height of each of the first end portion and second end portion is larger than the height in another portion of the second terminal.Type: ApplicationFiled: May 22, 2017Publication date: December 21, 2017Applicant: SEIKO EPSON CORPORATIONInventors: Yoshikazu TAKAHASHI, Masanobu SHOJI
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Publication number: 20160177260Abstract: The present invention provides a method of more efficiently producing a high-quality dopaminergic neuron from neural progenitor cells, specifically, a production method of a dopaminergic neuron including a step of culturing neural progenitor cells in a medium containing (i) a cAMP analogue and (ii) a MEK inhibitor. Moreover, the present invention also provides a medicament containing a dopaminergic neuron obtained by the method, and a reagent and a kit to be used for the method.Type: ApplicationFiled: August 6, 2014Publication date: June 23, 2016Inventor: Masanobu SHOJI
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Patent number: 9157069Abstract: Disclosed is a production method of pancreatic hormone-producing cells in a form that mimicks the pancreatogenesis, the method comprising subjecting stem cells to the following steps: (1) cultivating stem cells in a medium containing a Rho kinase inhibitor, (2) cultivating the cells obtained in (1) in a medium containing a GSK3 inhibitor, (3) cultivating the cells obtained in (2) in a medium containing GSK3 inhibitor and an activator of activin receptor-like kinase-4,7, (4) forming a cell mass from the cells obtained in (3), and cultivating the cell mass in a suspension state in a medium, (5) cultivating the cells obtained in (4) in a medium containing a retinoic acid receptor agonist, an inhibitor of AMP-activated protein kinase and/or activin receptor-like kinase-2,3,6, an inhibitor of activin receptor-like kinase-4,5,7 and a cell growth factor, and (6) cultivating the cells obtained in (5).Type: GrantFiled: August 8, 2011Date of Patent: October 13, 2015Assignee: Takeda Pharmaceutical Company LimitedInventors: Masaki Hosoya, Masanobu Shoji
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Patent number: 8932853Abstract: The present invention provides a method of more efficiently producing pancreas cells, particularly pancreatic hormone-producing cells, a method of stably producing pancreas cells in a large amount by more efficiently inducing differentiation of stem cells into pancreas cells, a medicament containing a pancreas cells and a screening method using the cells.Type: GrantFiled: December 28, 2010Date of Patent: January 13, 2015Assignee: Takeda Pharmaceutical Company LimitedInventors: Masaki Hosoya, Yuya Kunisada, Masanobu Shoji, Noriko Yamazoe
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Publication number: 20130210060Abstract: Disclosed is a production method of pancreatic hormone-producing cells in a form that mimics the pancreatogenesis, the method comprising subjecting stem cells to the following steps: (1) cultivating stem cells in a medium containing a Rho kinase inhibitor, (2) cultivating the cells obtained in (1) in a medium containing a GSK3 inhibitor, (3) cultivating the cells obtained in (2) in a medium containing GSK3 inhibitor and an activator of activin receptor-like kinase-4,7, (4) forming a cell mass from the cells obtained in (3), and cultivating the cell mass in a suspension state in a medium, (5) cultivating the cells obtained in (4) in a medium containing a retinoic acid receptor agonist, an inhibitor of AMP-activated protein kinase and/or activin receptor-like kinase-2,3,6, an inhibitor of activin receptor-like kinase-4,5,7 and a cell growth factor, and (6) cultivating the cells obtained in (5).Type: ApplicationFiled: August 8, 2011Publication date: August 15, 2013Applicant: TAKEDA PHARMACEUTICAL COMPANY LIMITEDInventors: Masaki Hosoya, Masanobu Shoji
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Publication number: 20130022986Abstract: The present invention provides a method of more efficiently producing pancreas cells, particularly pancreatic hormone-producing cells, a method of stably producing pancreas cells in a large amount by more efficiently inducing differentiation of stem cells into pancreas cells, a medicament containing a pancreas cells and a screening method using the cells.Type: ApplicationFiled: December 28, 2010Publication date: January 24, 2013Applicant: Takeda Pharmaceutical Company LimitedInventors: Masaki Hosoya, Yuya Kunisada, Masanobu Shoji, Noriko Yamazoe
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Publication number: 20120142005Abstract: A method for screening for a substance capable of regulating the regeneration, proliferation or differentiation of a cell or an organ, which comprises the steps of: (1) allowing a cell having a regenerative, proliferative or differentiative capability to form an embryoid body; (2) treating the embryoid body produced in step (1) with a digestive enzyme to prepare single cells from the embryoid body; (3) seeding the cells prepared in step (2) onto an adhesive plate, and adding a candidate substance to the plate to perform adhesion culturing of the cells on the plate; (4) conducting quantitative and simultaneous analysis of the levels of expression of at least two types of genes involved in the regeneration, proliferation or differentiation of cells after the adhesion culturing of step (3); and (5) evaluating the influence of the candidate substance on the regeneration, proliferation or differentiation of cells based on the results of the quantitative analysis obtained in step (4).Type: ApplicationFiled: May 25, 2010Publication date: June 7, 2012Applicant: TAKEDA PHARMACEUTICAL COMPANY LIMITEDInventors: Masaki Hosoya, Yuya Kunisada, Masanobu Shoji
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Patent number: 8125062Abstract: Lead frames and their fabricating method which reduce generation of defects in the process of fabricating semiconductor devices, in particular connection defects in wire bonding, thereby improving the product yield and reliability, and semiconductor devices using the lead frames and their fabricating method are provided. A method for fabricating a lead frame is characterized in including a process of forming a substrate equipped with a convex portion, and a metal layer having a first portion that overlaps a first surface included in the convex portion and a second portion that extends from the first portion and does not overlap the first surface, and a process of bending the metal layer such that the second portion of the metal layer overlaps a second surface included in the convex portion that intersects the first surface.Type: GrantFiled: March 15, 2010Date of Patent: February 28, 2012Assignee: Seiko Epson CorporationInventors: Masanobu Shoji, Toru Fujita
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Patent number: 7875988Abstract: A substrate for fixing an integrated circuit element includes: a plurality of metal columns that are aligned in a longitudinal direction and a lateral direction in a planar view, each of the plurality of metal columns having a first face and a second face facing opposite direction to the first face; and a connecting part that connects the plurality of metal columns one another at a part of each of the plurality of metal columns between the first face and the second face. In the substrate, a recognition mark is formed on the first face of one of the plurality of metal columns.Type: GrantFiled: July 7, 2008Date of Patent: January 25, 2011Assignee: Seiko Epson CorporationInventors: Masanobu Shoji, Toru Fujita
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Publication number: 20100301465Abstract: Lead frames and their fabricating method which reduce generation of defects in the process of fabricating semiconductor devices, in particular connection defects in wire bonding, thereby improving the product yield and reliability, and semiconductor devices using the lead frames and their fabricating method are provided. A method for fabricating a lead frame is characterized in including a process of forming a substrate equipped with a convex portion, and a metal layer having a first portion that overlaps a first surface included in the convex portion and a second portion that extends from the first portion and does not overlap the first surface, and a process of bending the metal layer such that the second portion of the metal layer overlaps a second surface included in the convex portion that intersects the first surface.Type: ApplicationFiled: March 15, 2010Publication date: December 2, 2010Applicant: SEIKO EPSON CORPORATIONInventors: Masanobu SHOJI, Toru FUJITA
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Patent number: 7807498Abstract: A substrate for fixing an integrated circuit (IC) element comprises: a substrate for fixing an integrated circuit element includes: a plurality of metal posts that are aligned in a longitudinal direction and a lateral direction in plan view, each of the plurality of metal posts having a first surface and a second surface facing an opposite direction to the first surface, the plurality of metal posts being configured identically; and a joining section that joins each of the plurality of metal posts together at a portion of each of the plurality of metal posts between the first surface and the second surface.Type: GrantFiled: July 10, 2008Date of Patent: October 5, 2010Assignee: Seiko Epson CorporationInventors: Masanobu Shoji, Toru Fujita
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Publication number: 20090302466Abstract: A semiconductor device includes a first metal post that has a first face, a second metal post that has a second face, a first plated layer that is provided on the first face, the first plated layer being discontiguous with an outer edge of the first face, a second plated layer that is provided on the second face, the second plated layer being discontiguous with an outer edge of the second face, an integrated circuit element that is fixed on the first face; a conductor that electrically connects the integrated circuit element with the second metal post, and a resin that seals the integrated circuit element and the conductor.Type: ApplicationFiled: May 21, 2009Publication date: December 10, 2009Applicant: SEIKO EPSON CORPORATIONInventors: Masanobu SHOJI, Toru FUJITA
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Patent number: 7608479Abstract: A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section.Type: GrantFiled: January 17, 2006Date of Patent: October 27, 2009Assignee: Seiko Epson CorporationInventors: Hirohisa Nakayama, Shiro Sato, Masanobu Shoji, Hitoshi Nosaka
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Publication number: 20090243095Abstract: A substrate on which an IC element is fixed includes: a plurality of metal posts arranged in a plurality of columns in a lengthwise direction and in a plurality of rows in a crosswise direction when viewed in a plan view, the plurality of metal posts having first faces and second faces that face an opposite side to a side that the first faces face; first marks each of the first marks being disposed on extending lines of the plurality of columns; and second marks, each of the second marks being disposed on extending lines of the plurality of rows.Type: ApplicationFiled: March 23, 2009Publication date: October 1, 2009Applicant: SEIKO EPSON CORPORATIONInventors: Toru FUJITA, Masanobu SHOJI
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Publication number: 20090034225Abstract: A substrate for fixing an integrated circuit element includes: a plurality of metal columns that are aligned in a longitudinal direction and a lateral direction in a planar view, each of the plurality of metal columns having a first face and a second face facing opposite direction to the first face; and a connecting part that connects the plurality of metal columns one another at a part of each of the plurality of metal columns between the first face and the second face. In the substrate, a recognition mark is formed on the first face of one of the plurality of metal columns.Type: ApplicationFiled: July 7, 2008Publication date: February 5, 2009Applicant: SEIKO EPSON CORPORATIONInventors: Masanobu SHOJI, Toru FUJITA
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Publication number: 20090032943Abstract: A substrate for fixing an integrated circuit (IC) element comprises: a substrate for fixing an integrated circuit element includes: a plurality of metal posts that are aligned in a longitudinal direction and a lateral direction in plan view, each of the plurality of metal posts having a first surface and a second surface facing an opposite direction to the first surface, the plurality of metal posts being configured identically; and a joining section that joins each of the plurality of metal posts together at a portion of each of the plurality of metal posts between the first surface and the second surface.Type: ApplicationFiled: July 10, 2008Publication date: February 5, 2009Applicant: SEIKO EPSON CORPORATIONInventors: Masanobu SHOJI, Toru FUJITA
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Publication number: 20060160347Abstract: A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section.Type: ApplicationFiled: January 17, 2006Publication date: July 20, 2006Applicant: SEIKO EPSON CORPORATIONInventors: Hirohisa Nakayama, Shiro Sato, Masanobu Shoji, Hitoshi Nosaka