Abstract: A first fuse unit and a second fuse unit each have the same configuration. A rectification element is coupled in parallel with a fuse element. A first transistor has its drain coupled to a second end of the fuse element, its source coupled to a second line, and its gate coupled to a program terminal. A second transistor has its source coupled to the second end of the fuse element, its drain coupled to the output terminal, and its gate coupled to the test terminal. A third transistor has its drain coupled to the output terminal, and its source coupled to the second line.

Abstract: A power-on reset circuit supplies a reset pulse to a sequential circuit to be initialized. A latch circuit includes a first inversion circuit and a second inversion circuit structured to invert and amplify a signal input thereto, with an output node of the first inversion circuit connected to an input node of the second inversion circuit, and with an output node of the second inversion circuit connected to an input node of the first inversion circuit. A decision circuit receives the first signal from the output node of the first inversion circuit and the second signal from the output node of the second inversion circuit and generates a reset pulse on the basis of the first signal and the second signal.

Abstract: A DCO is configured such that, during a period in which a selection signal is asserted, a ring oscillator is formed so as to oscillate at a frequency that corresponds to a control code, and such that, during a period in which the selection signal SEL is negated, an injection edge based on a reference clock can be injected. During the startup period of a PLL circuit, a controller repeats a cycle including (i) a process in which the selection signal is asserted so as to oscillate the DCO, and phase comparison is made between an oscillator clock and the reference clock, and (ii) a process in which the selection signal is negated so as to stop the DCO, and the control code is updated by a binary search based on a result of the phase comparison.

Abstract: A controller controls multiple parallel-coupled power transistors. A correction amount calculation unit generates a reference value based on multiple detection values, each of which has a correlation with the switching loss of corresponding one of the multiple power transistors, and generates multiple correction amounts such that the multiple detection values approach the reference value. A gate signal generating unit generates multiple gate signals based on a control instruction and the multiple correction amounts.

Abstract: A primary transmitter drives a primary-side input of an isolation barrier in response to a transition of an input signal. A secondary receiver generates an output signal having a logical value that corresponds to a signal that occurs at a secondary-side output of the isolation barrier. A secondary transmitter drives a secondary-side input of the isolation barrier based on the output signal. A primary receiver generates a return signal having a logical value that corresponds to a signal that occurs at a primary-side output of the isolation barrier. The primary transmitter repeatedly drives the primary-side input of the isolation barrier until the logical value of the input signal matches that of the return signal.

Abstract: A transformer includes a primary winding and a secondary winding. A transmitting circuit is coupled to a primary winding of a transformer and supplies a current signal to the primary winding with a polarity that changes in response to a change of the input signal level. A latch circuit is arranged such that its set terminal is coupled to one end of the secondary winding of the transformer, and its reset terminal is coupled to the other end of the secondary winding of the transformer. A first switch is arranged between a common voltage node at which a common voltage occurs and the set terminal. When the output of the latch circuit is high, the first switch is turned on. A second switch is arranged between the common voltage node and the reset terminal. When the output of the latch circuit is low, the second switch is turned on.

Abstract: A semiconductor integrated circuit includes a current mirror circuit, wherein the current mirror circuit includes: an input node and an output node; a plurality of transistors; a switch circuit configured to be capable of selectively connecting each of the plurality of transistors to the input node or the output node; and a controller configured to control the switch circuit such that M (where M is an integer) transistors among the plurality of transistors are connected to the input node and N (where N is an integer) transistors among the plurality of transistors are connected to the output node, wherein the controller switches a combination of the M transistors and a combination of the N transistors in a time division manner.

Abstract: A DCO is configured such that, during a period in which a selection signal is asserted, a ring oscillator is formed so as to oscillate at a frequency that corresponds to a control code, and such that, during a period in which the selection signal SEL is negated, an injection edge based on a reference clock can be injected. During the startup period of a PLL circuit, a controller repeats a cycle including (i) a process in which the selection signal is asserted so as to oscillate the DCO, and phase comparison is made between an oscillator clock and the reference clock, and (ii) a process in which the selection signal is negated so as to stop the DCO, and the control code is updated by a binary search based on a result of the phase comparison.

Abstract: Disclosed herein is a voltage comparator including a first capacitor, a first inverter and a first switch connected in series and provided between both ends of the first capacitor, a second inverter connected in parallel with the first inverter, a second switch provided between an input and an output of the first inverter, a third switch provided between an input and an output of the second inverter, a second capacitor provided between the output of the first inverter and the input of the second inverter, a third capacitor provided between the output of the second inverter and the input of the first inverter, and a fourth switch provided in one of a position between an upper electrode of the first capacitor and a power supply line and a position between a lower electrode of the first capacitor and a ground line.

Abstract: An output terminal of a power supply circuit is coupled to a load. A control circuit charges multiple intermediate capacitors using an input voltage in a time-sharing manner. Furthermore, the control circuit selects at least one intermediate capacitor that is not being charged from among the multiple intermediate capacitors, and couples the intermediate capacitor thus selected to an output capacitor.

Abstract: A frequency variable oscillator generates a clock having a frequency according to a control signal. A reference current source generates a reference current. A path selector distributes the reference current to a first path and a second path in a time-sharing manner in synchronization with the clock. An F/V conversion circuit includes a capacitor connected to the first path, and charges or discharges the capacitor with the reference current and generates a detection voltage. The reference voltage source includes a resistor connected to the second path, and outputs a reference voltage according to a voltage across the resistor. A feedback circuit adjusts a control signal so that the detection voltage approaches the reference voltage.

Abstract: A variable-frequency oscillator generates an oscillator clock having a frequency that corresponds to a control signal. A programmable frequency divider divides the oscillator clock, so as to generate a divided clock. A F/V converter circuit includes a capacitor and a switch that switches at a frequency that corresponds to the divided clock, and generates a detection voltage that corresponds to a reference current. A reference voltage source outputs a reference voltage that corresponds to the electric potential that occurs at the resistor due to a reference current. A feedback circuit adjusts a control signal such that the detection voltage approaches the reference voltage. A correction circuit changes the frequency-dividing ratio of the programmable frequency divider based on a modulation signal modulated according to a correction coefficient that corresponds to the temperature.

Abstract: Disclosed here is a PLL circuit that is an injection-locked PLL circuit. The PLL circuit includes a variable frequency oscillator configured in such a manner that a ring oscillator is formed during a period in which a window signal is negated and an injection edge based on a reference clock is allowed to be injected during a period in which the window signal is asserted, a feedback circuit that controls the variable frequency oscillator in such a manner that an oscillation frequency of the variable frequency oscillator gets closer to a target frequency according to the reference clock, and a window generator that receives an internal clock of the variable frequency oscillator and cuts out one pulse to generate the window signal.

Abstract: Disclosed here is a PLL circuit that is an injection-locked PLL circuit. The PLL circuit includes a variable frequency oscillator configured in such a manner that a ring oscillator is formed during a period in which a window signal is negated and an injection edge based on a reference clock is allowed to be injected during a period in which the window signal is asserted, a feedback circuit that controls the variable frequency oscillator in such a manner that an oscillation frequency of the variable frequency oscillator gets closer to a target frequency according to the reference clock, and a window generator that receives an internal clock of the variable frequency oscillator and cuts out one pulse to generate the window signal.

Abstract: Disclosed herein is a voltage comparator including a first capacitor, a first inverter and a first switch connected in series and provided between both ends of the first capacitor, a second inverter connected in parallel with the first inverter, a second switch provided between an input and an output of the first inverter, a third switch provided between an input and an output of the second inverter, a second capacitor provided between the output of the first inverter and the input of the second inverter, a third capacitor provided between the output of the second inverter and the input of the first inverter, and a fourth switch provided in one of a position between an upper electrode of the first capacitor and a power supply line and a position between a lower electrode of the first capacitor and a ground line.

Abstract: An output terminal of a power supply circuit is coupled to a load. A control circuit charges multiple intermediate capacitors using an input voltage in a time-sharing manner. Furthermore, the control circuit selects at least one intermediate capacitor that is not being charged from among the multiple intermediate capacitors, and couples the intermediate capacitor thus selected to an output capacitor.

Abstract: A variable-frequency oscillator generates an oscillator clock having a frequency that corresponds to a control signal. A programmable frequency divider divides the oscillator clock, so as to generate a divided clock. A F/V converter circuit includes a capacitor and a switch that switches at a frequency that corresponds to the divided clock, and generates a detection voltage that corresponds to a reference current. A reference voltage source outputs a reference voltage that corresponds to the electric potential that occurs at the resistor due to a reference current. A feedback circuit adjusts a control signal such that the detection voltage approaches the reference voltage. A correction circuit changes the frequency-dividing ratio of the programmable frequency divider based on a modulation signal modulated according to a correction coefficient that corresponds to the temperature.

Abstract: A frequency variable oscillator generates a clock having a frequency according to a control signal. A reference current source generates a reference current. A path selector distributes the reference current to a first path and a second path in a time-sharing manner in synchronization with the clock. An F/V conversion circuit includes a capacitor connected to the first path, and charges or discharges the capacitor with the reference current and generates a detection voltage. The reference voltage source includes a resistor connected to the second path, and outputs a reference voltage according to a voltage across the resistor. A feedback circuit adjusts a control signal so that the detection voltage approaches the reference voltage.

Abstract: During a period in which a first signal S1 and second signal S2 are both set to a first level, an initializing circuit initializes a capacitor voltage. Multiple circuit units are coupled in parallel between an intermediate line and a second line. An output circuit generates an output signal SOUT that changes level when the capacitor voltage crosses a predetermined threshold value VTH. Each circuit unit includes a resistor Rg and first path arranged in series between the intermediate and second lines and a second path parallel to the first path. The first path is configured to turn on when the first signal S1 is the second level and the corresponding bit of an input code is a first value. The second path is configured to turn on when the second signal S2 is the second level and the corresponding bit of the input code is a second value.

Abstract: During a period in which a first signal S1 and second signal S2 are both set to a first level, an initializing circuit initializes a capacitor voltage. Multiple circuit units are coupled in parallel between an intermediate line and a second line. An output circuit generates an output signal SOUT our that changes level when the capacitor voltage crosses a predetermined threshold value VTH. Each circuit unit includes a resistor Rg and first path arranged in series between the intermediate and second lines and a second path parallel to the first path. The first path is configured to turn on when the first signal S1 is the second level and the corresponding bit of an input code is a first value. The second path is configured to turn on when the second signal S2 is the second level and the corresponding bit of the input code is a second value.