Patents by Inventor Masanori Fukumoto
Masanori Fukumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230073265Abstract: A feature acquiring section 100 obtains feature data of a target person. A matching degree deriving section 110 derives a matching degree between the feature data and feature data of a registered user stored in a feature amount database 120. An identifying section 130 determines that the target person is the registered user in a case where the matching degree is greater than or equal to a first threshold, and determines that the target person is not the registered user in a case where the matching degree is less than a second threshold smaller than the first threshold. An action management section 140 sets an action mode of an acting subject according to the matching degree.Type: ApplicationFiled: February 12, 2021Publication date: March 9, 2023Inventors: Shinichi HONDA, Akio OHBA, Hiroyuki SEGAWA, Masanori FUKUMOTO, Akihiko SUGAWARA
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Patent number: 5693557Abstract: A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.Type: GrantFiled: January 24, 1996Date of Patent: December 2, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shuji Hirao, Hisashi Ogawa, Yuka Terai, Mitsuru Sekiguchi, Masanori Fukumoto, Isao Miyanaga
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Patent number: 5677220Abstract: A surface region of a P-type semiconductor substrate is defined by an isolation into plural active regions at which a semiconductor element is to be formed. A first diffusion region such as a drain region, a second diffusion region such as a source region, and a wiring member such as a word line are arranged at each active region. The surface of the word line is covered with a first insulating layer. A second insulating layer is provided, in which a region including in common each overhead region on at least two second diffusion regions is removed, leaving an overhead region on the first diffusion region. Provided above the second diffusion region is a conductive member such as a capacity storage electrode, a bit line. A contact member which connects the conductive member and the second diffusion region is formed at a region where the second insulating layer is removed.Type: GrantFiled: June 7, 1995Date of Patent: October 14, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomofumi Shono, Akira Asai, Masanori Fukumoto
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Patent number: 5661068Abstract: A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.Type: GrantFiled: June 6, 1995Date of Patent: August 26, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shuji Hirao, Hisashi Ogawa, Yuka Terai, Mitsuru Sekiguchi, Masanori Fukumoto, Isao Miyanaga
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Patent number: 5633211Abstract: The characteristic of semiconductor devices is satisfactorily maintained because the planarization of a dielectric film of a semiconductor device is carried out at a lower flow temperature. In the case of a silicon dioxide film being a dielectric film, a network structure is composed of atoms of silicon which serve as a main constituent, and of atoms of oxygen which serve as a sub-constituent of a matrix of the dielectric film. These oxygen atoms are replaced by non-bridging constituents such as atoms of halogen including fluorine. This breaks a bridge, via an oxygen atom, between the silicon atoms, at a position where such a replacement takes place. In consequence, the viscosity of the dielectric film falls with the flow temperature. If, for example, part of the oxygen in a BPSG film is substituted by fluorine, this allows the dielectric film to flow at a lower temperature of 850.degree. C. The short channel effects can be suppressed.Type: GrantFiled: November 23, 1994Date of Patent: May 27, 1997Assignee: Matsushita Electric Industrial Co., Ld.Inventors: Shinichi Imai, Yuka Terai, Masanori Fukumoto, Kousaku Yano, Hiroyuki Umimoto, Shinji Odanaka, Yasuo Mizuno
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Patent number: 5474949Abstract: A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.Type: GrantFiled: January 26, 1993Date of Patent: December 12, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shuji Hirao, Hisashi Ogawa, Yuka Terai, Mitsuru Sekiguchi, Masanori Fukumoto, Isao Miyanaga
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Patent number: 5459341Abstract: A surface region of a P-type semiconductor substrate is defined by an isolation into plural active regions at which a semiconductor element is to be formed. A first diffusion region such as a drain region, a second diffusion region such as a source region, and a wiring member such as a word line are arranged at each active region. The surface of the word line is covered with a first insulating layer. A second insulating layer is provided, in which a region including in common each overhead region on at least two second diffusion regions is removed, leaving an overhead region on the first diffusion region. Provided above the second diffusion region is a conductive member such as a capacity storage electrode, a bit line. A contact member which connects the conductive member and the second diffusion region is formed at a region where the second insulating layer is removed.Type: GrantFiled: February 14, 1994Date of Patent: October 17, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomofumi Shono, Akira Asai, Masanori Fukumoto
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Patent number: 5449934Abstract: A semiconductor memory device with a storage capacitor is provided which accomplishes a large storage capacity together with a high component density, and facilitates the production. A switching transistor is formed locally in a semiconductor substrate. Formed over the transistor is an upper-level wire disposed over which is a storage capacitor. A storage capacitor contact passes through the upper-level wire. While ensuring a good capacity for the storage capacitor contact, the allowance of focus, too, can advantageously be obtained in simultaneously transferring a pattern of the upper-level wire onto the memory cell region as well as onto the peripheral circuit region. Particularly, by having the storage capacitor contact pass through a bit line, a drain and a source can symmetrically be arranged with a word line, like a memory cell with a bit-line-over-storage-capacitor organization cell. This eliminates an excess portion resulting in increasing the density.Type: GrantFiled: April 29, 1994Date of Patent: September 12, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomofumi Shono, Teruhito Ohnishi, Masanori Fukumoto
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Patent number: 5384276Abstract: A method of fabricating a semiconductor device is disclosed. The method comprises the steps of: forming a multi-layer film comprising two or more kinds of layers; performing first etching for patterning said multi-layer film under a first etching condition; and performing second etching for forming irregularities in the side faces of said patterned multi-layer film under a second etching condition.Type: GrantFiled: July 2, 1992Date of Patent: January 24, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hisashi Ogawa, Yutaka Nabeshima, Masanori Fukumoto
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Patent number: 5365095Abstract: A semiconductor memory device with a storage capacitor is provided which accomplishes a large storage capacity together with a high component density, and facilitates the production. A switching transistor is formed locally in a semiconductor substrate. Formed over the transistor is an upper-level wire disposed over which is a storage capacitor. A storage capacitor contact passes through the upper-level wire. While ensuring a good capacity for the storage capacitor contact, the allowance of focus, too, can advantageously be obtained in simultaneously transferring a pattern of the upper-level wire onto the memory cell region as well as onto the peripheral circuit region. Particularly, by having the storage capacitor contact pass through a bit line, a drain and a source can symmetrically be arranged with a word line, like a memory cell with a bit-line-over-storage-capacitor organization cell. This eliminates an excess portion resulting in increasing the density.Type: GrantFiled: February 18, 1993Date of Patent: November 15, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomofumi Shono, Teruhito Ohnishi, Masanori Fukumoto
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Patent number: 5275972Abstract: A fabrication method for a semiconductor integrated circuits which permits the self-aligned formation of contact windows without causing shorts or breaks in the interconnecting lines in the device is provided. After forming gate electrodes and source/drain regions of transistors on a semiconductor substrate, an etch-stop layer and a BPSG film are successively deposited over the gate electrodes and the source/drain regions. After a resist having a contact window pattern is formed on the BPSG film, an isotropic dry etching using a microwave plasma is performed to etch the BPSG film. According to the isotropic dry etching, the laterally etching rate in the BPSG film can be controlled by adjusting the RF power, and a silicon dioxide film can be used as the etch stop layer. After the BPSG flow process, the etch stop layer on the contact region is etched away to form contact windows.Type: GrantFiled: August 14, 1992Date of Patent: January 4, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hisashi Ogawa, Yasushi Naito, Masanori Fukumoto
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Patent number: 5242852Abstract: In a method for manufacturing DRAMs in a stacked memory cell type, an edge portion of each bit line is bared upon etching a first insulating film, the bared edge portion is etched to from an opening and an inner peripheral surface of the opening is covered by a second insulating film. There is also disclosed a method wherein second and third insulating films and second conductive film are stacked on a first insulating film, a second conductive film is formed and the second conductive film and the first conductive film are partially etched whereby the unetched portions of the first conductive film serve as electrode planes of charge storage electrodes.Type: GrantFiled: September 11, 1992Date of Patent: September 7, 1993Assignee: Matsushita Electric Industrial Co. Ltd.Inventors: Kazuhiro Matsuyama, Masanori Fukumoto, Yasushi Naito, Hisashi Ogawa, Shozo Okada
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Patent number: 5164337Abstract: A method of fabricating a semiconductor device is disclosed. The method comprises the steps of: forming a multi-layer film comprising two or more kinds of layers; performing first etching for patterning said multi-layer film under a first etching condition; and performing second etching for forming irregularities in the side faces of said patterned multi-layer film under a second etching condition.Type: GrantFiled: October 31, 1990Date of Patent: November 17, 1992Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hisashi Ogawa, Yutaka Nabeshima, Masanori Fukumoto
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Patent number: 5128274Abstract: There are provided semiconductor devices including a semiconductor substrate having a surface divided into a first and second regions, a plurality of active regions formed on the substrate, and a local-oxidized (LOCOS) insulating film formed on the substrate as an isolation region for electrical isolation of the active regions from each other. The LOCOS insulating film is thicker in the first region than in the second region, or the LOCOS insulating film has a difference in level based on the thickness change in the vicinity of the boundary between the first and second regions. Also provided are various methods for producing such semiconductor devices.Type: GrantFiled: June 26, 1991Date of Patent: July 7, 1992Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiki Yabu, Masanori Fukumoto, Yasushi Naito
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Patent number: 5047815Abstract: A semiconductor memory device includes a capacitor and an insulating separation area in a trench formed around a switching transistor, with a storage electrode of the capacitor being sandwiched between an upper and a lower cell plate electrode to reduce leakage current due to the parasitic MOS transistor effect in the trench sidewall along the channel in the switching transistor and leakage current due to the gate-controlled diode effect in the trench sidewall. Also, a method is disclosed for manufacturing such semiconductor memory device.Type: GrantFiled: August 14, 1989Date of Patent: September 10, 1991Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mitsuo Yasuhira, Takatoshi Yasui, Kazuhiro Matsuyama, Hideyuki Iwata, Masanori Fukumoto