Patents by Inventor Masanori Hayashikoshi
Masanori Hayashikoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10108249Abstract: The memory power consumption is reduced more than in the past by performing a power control suitably for a nonvolatile memory. A memory control circuit is provided with a first register group for a CPU to perform separately initial setting of the operation mode (power OFF, standby, and power ON) of plural banks included in a nonvolatile memory, for every task of a program executed by the CPU, and an access determination unit which determines a bank to which an access from the CPU takes place, on the basis of the access address for instruction fetching and the kind of the fetched instruction. The memory control circuit switches the operation mode of each of the banks on the basis of the setting value of the first register group, and the determination result of the access determination unit.Type: GrantFiled: April 1, 2014Date of Patent: October 23, 2018Assignee: Renesas Electronics CorporationInventors: Seiji Seki, Masanori Hayashikoshi, Kiyoshi Nakakimura
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Patent number: 9977664Abstract: An application process is switched between asymmetric processor cores having no compatibility in instruction set architectures so that the process can be continuously executed. In an information processing device, when a request to switch an execution subject is generated while a first processor core is executing an application program, a switch process code makes the first processor core specify a basic block being executed at present. The switch process code makes the first processor core execute a first execution code until a branch instruction at the end of the specified basic block, and makes a second processor core execute a second execution code from an instruction at the head of a basic block to be executed next to the specified basic block.Type: GrantFiled: April 2, 2014Date of Patent: May 22, 2018Assignee: Renesas Electronics CorporationInventors: Masakatsu Toyama, Masanori Hayashikoshi
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Publication number: 20140304490Abstract: An application process is switched between asymmetric processor cores having no compatibility in instruction set architectures so that the process can be continuously executed. In an information processing device, when a request to switch an execution subject is generated while a first processor core is executing an application program, a switch process code makes the first processor core specify a basic block being executed at present. The switch process code makes the first processor core execute a first execution code until a branch instruction at the end of the specified basic block, and makes a second processor core execute a second execution code from an instruction at the head of a basic block to be executed next to the specified basic block.Type: ApplicationFiled: April 2, 2014Publication date: October 9, 2014Applicant: Renesas Electronics CorporationInventors: Masakatsu TOYAMA, Masanori HAYASHIKOSHI
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Publication number: 20140298056Abstract: The memory power consumption is reduced more than in the past by performing a power control suitably for a nonvolatile memory. A memory control circuit is provided with a first register group for a CPU to perform separately initial setting of the operation mode (power OFF, standby, and power ON) of plural banks included in a nonvolatile memory, for every task of a program executed by the CPU, and an access determination unit which determines a bank to which an access from the CPU takes place, on the basis of the access address for instruction fetching and the kind of the fetched instruction. The memory control circuit switches the operation mode of each of the banks on the basis of the setting value of the first register group, and the determination result of the access determination unit.Type: ApplicationFiled: April 1, 2014Publication date: October 2, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Seiji SEKI, Masanori HAYASHIKOSHI, Kiyoshi NAKAKIMURA
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Patent number: 8508986Abstract: A semiconductor device having first and second digit line drivers and a bit line driver. When the address of one segment has been input from the outside, a segment decoder selects one segment corresponding to the address and couples the same to the selected first digit line driver. When the addresses of two or more segments have been input from the outside, the segment decoder selects two or more segments corresponding to the addresses and couples the selected two or more segments to the respective digital line drivers.Type: GrantFiled: July 22, 2011Date of Patent: August 13, 2013Assignee: Renesas Electronics CorporationInventors: Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Masanori Hayashikoshi
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Publication number: 20120075921Abstract: A semiconductor device using a segment writing method capable of achieving a normal write operation is provided. The first DL driver and the second DL driver each cause a magnetizing current to flow through a digit line of a selected block. A BL driver causes a write current to flow in a direction corresponding to the logic of a data signal to all bit lines in a selected segment, and writes the data signal to a memory cell of the selected block. A segment decoder, when the address of one segment has been input from the outside, selects one segment corresponding to the address and couples the same to the selected first DL driver, and the segment decoder, when the addresses of two or more segments have been input from the outside, selects two or more segments corresponding to the addresses and couples the selected two or more segments to the first DL driver and the second DL driver, respectively.Type: ApplicationFiled: July 22, 2011Publication date: March 29, 2012Inventors: Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Masanori Hayashikoshi
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Patent number: 6483761Abstract: The semiconductor memory device in accordance with the present invention allows evaluation of input/output terminal dependency of noise characteristic at the time of data output, it has a normal operation mode and a test mode, and includes a plurality of output buffers and selecting means for selectively activating at least one output buffer among the plurality of output buffers in the test mode.Type: GrantFiled: October 3, 2001Date of Patent: November 19, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Akamatsu, Masanori Hayashikoshi
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Publication number: 20020018383Abstract: The semiconductor memory device in accordance with the present invention allows evaluation of input/output terminal dependency of noise characteristic at the time of data output, it has a normal operation mode and a test mode, and includes a plurality of output buffers and selecting means for selectively activating at least one output buffer among the plurality of output buffers in the test mode.Type: ApplicationFiled: October 3, 2001Publication date: February 14, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hiroshi Akamatsu, Masanori Hayashikoshi
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Patent number: 6337814Abstract: A test mode reference potential generating circuit outputs a reference potential from an output node by activation of a test mode signal. When a sample signal is in an activated state, a transfer gate is turned on, and a capacitor stores the reference potential. When the test is being conducted, the transfer gate is turned off by inactivation of the sample signal, and thus the reference potential stored in the capacitor is output from a node. Thus, the semiconductor memory device according to the present invention can generate a stable reference potential during the test mode.Type: GrantFiled: July 23, 2001Date of Patent: January 8, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Susumu Tanida, Masanori Hayashikoshi
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Patent number: 6304503Abstract: The semiconductor memory device in accordance with the present invention allows evaluation of input/output terminal dependency of noise characteristic at the time of data output, it has a normal operation mode and a test mode, and includes a plurality of output at buffers and selecting means for selectively activating at least one output buffer among the plurality of output buffers in the test mode.Type: GrantFiled: January 28, 1999Date of Patent: October 16, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Akamatsu, Masanori Hayashikoshi
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Patent number: 6097180Abstract: The level shifter circuit of an internal down converter includes a P channel MOS transistor constituting a resistance component, and a resistor constituting a resistance component. The temperature coefficient of resistance component is set larger than the temperature coefficient of resistance component so that the output voltage of level shifter circuit has a negative temperature characteristic. If a reference voltage generated by reference voltage generation circuit decreases when operating at a high temperature, the output voltage of level shifter circuit decreases as well. Thus, change in an internal voltage due to change in the operation temperature can be compensated.Type: GrantFiled: July 15, 1999Date of Patent: August 1, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masaki Tsukude, Masanori Hayashikoshi
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Patent number: 6088819Abstract: In a DRAM, a boosted voltage Vpp is applied to a selected word line WL1 in a normal mode. In a test mode, a power supply voltage Vcc at a level lower than Vpp level is applied onto selected word line WL1. High data written into memory cell in the test mode of the DRAM is at the level lower than that of the high data written into memory cell in the normal mode. Therefore, a time before an H.fwdarw.L error occurs can be reduced, and a test time can be reduced.Type: GrantFiled: August 13, 1997Date of Patent: July 11, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yukinobu Adachi, Hiromi Okimoto, Masanori Hayashikoshi
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Patent number: 6011428Abstract: The level shifter circuit of an internal down converter includes a P channel MOS transistor constituting a resistance component, and a resistor constituting a resistance component. The temperature coefficient of resistance component is set larger than the temperature coefficient of resistance component so that the output voltage of level shifter circuit has a negative temperature characteristic. If a reference voltage generated by reference voltage generation circuit decreases when operating at a high temperature, the output voltage of level shifter circuit decreases as well. Thus, change in an internal voltage due to change in the operation temperature can be compensated.Type: GrantFiled: October 14, 1993Date of Patent: January 4, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masaki Tsukude, Masanori Hayashikoshi
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Patent number: 5986915Abstract: A column select line includes a first layer column select line and a second layer column select line formed above the first layer column select line and connected thereto at any point. Furthermore, clamping circuits each for clamping each word line of paired main word lines at a constant potential are provided in a semiconductor memory device having main and secondary word line structure. With such a structure, malfunction due to multiselection of memory cells can be avoided even when the column select line or the paired main word lines is disconnected.Type: GrantFiled: September 17, 1998Date of Patent: November 16, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiromi Okimoto, Masanori Hayashikoshi, Youichi Tobita
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Patent number: 5956281Abstract: A switching circuit is provided which activates a shallow level detector and inactivates a deep level detector when a disturb test signal or a self refresh signal is activated. Accordingly, a shallow substrate voltage at the same level as a detection level of the shallow level detector can be generated by a substrate voltage generating circuit not only in a disturb test mode but also in a self refresh mode. As a result, the area penalty due to the shallow level detector is reduced.Type: GrantFiled: March 16, 1998Date of Patent: September 21, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Jun Nakai, Masanori Hayashikoshi
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Patent number: 5835419Abstract: A semiconductor memory device includes: subarrays having memory cells each arranged at cross points of a plurality of bit lines and a plurality of word lines; a row decoder for selecting among the word lines; a column decoder for supplying a select signal to transfer gates for selecting among paired bit lines; and a clamping circuit for fixing the potential of a column select line at a constant potential before the column decoder is activated.Type: GrantFiled: February 27, 1997Date of Patent: November 10, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tooru Ichimura, Hiromi Okimoto, Masanori Hayashikoshi, Youichi Tobita
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Patent number: 5825694Abstract: A column select line includes a first layer column select line and a second layer column select line formed above the first layer column select line and connected thereto at any point. Furthermore, clamping circuits each for clamping each word line of paired main word lines at a constant potential are provided in a semiconductor memory device having main and secondary word line structure. With such a structure, malfunction due to multiselection of memory cells can be avoided even when the column select line or the paired main word lines is disconnected.Type: GrantFiled: February 26, 1997Date of Patent: October 20, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiromi Okimoto, Masanori Hayashikoshi, Youichi Tobita
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Patent number: 5691661Abstract: A pulse signal generating circuit includes a ring oscillator and an internal voltage generating circuit. The internal voltage generating circuit generates an internal voltage depending on an operation temperature. The internal voltage is low at a normal temperature, and is high at a high temperature. Each inverter in the ring oscillator is driven by the internal voltage supplied from the internal voltage generating circuit. Thereby, a period of a pulse signal increases at a normal temperature, and decreases at a high temperature.Type: GrantFiled: June 2, 1995Date of Patent: November 25, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tatsuya Fukuda, Shigeru Mori, Masanori Hayashikoshi, Seiji Sawada
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Patent number: 5666317Abstract: When a disturb refresh mode is detected by a mode detecting circuit, a row decoder control circuit simultaneously activates every several word lines of a memory cell array of a block selected by an operation block selecting circuit through a row decoder and a driving circuit, reads out data written in a normal mode, and determines a memory cell having a threshold value lower than that of a design value upon determination of match of read data and written data.Type: GrantFiled: February 23, 1996Date of Patent: September 9, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Susumu Tanida, Kazutoshi Hirayama, Tomio Suzuki, Masanori Hayashikoshi
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Patent number: RE36089Abstract: Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.Type: GrantFiled: May 23, 1996Date of Patent: February 9, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tsukasa Ooishi, Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi, Shinji Kawai, Mikio Asakura, Masaki Tsukude, Katsuhiro Suma, Shigeki Tomishima, Kazuyasu Fujishima