Patents by Inventor Masanori Hiraoka

Masanori Hiraoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990260
    Abstract: The present invention is a method for producing a rare earth magnet, including preparing a magnetic powder and a modifier powder, mixing them to obtain a mixed powder, compression-molding the mixed powder in a magnetic field to obtain a magnetic-field molded body, and pressure-sintering the magnetic-field molded body to obtain a sintered body, wherein the magnetic powder includes a first particle group and a second particle group, the D50 values of the first particle group and the second particle group are denoted by d1 ?m and d2 ?m, respectively, d1 and d2 satisfy the relationship of 0.350?d2/d1?0.500, and the ratio between the total volume of the first particle group and the total volume of the second particle group is from 9:1 to 4:1; and a rare earth magnet obtained by the production method.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: May 21, 2024
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, NICHIA CORPORATION
    Inventors: Masaaki Ito, Motoki Hiraoka, Reimi Tabuchi, Hisashi Maehara, Masanori Okanan
  • Patent number: 5917993
    Abstract: Disclosed is a color image processing apparatus, for converting source data into bit map data of each primary color, used for a color image outputting mechanism for expressing secondary colors by superposing a plurality of primary colors. This color image processing apparatus includes bit map memory having a plurality of planes, provided corresponding to the plurality of primary colors, for storing bit map data of the respective primary colors. A write control circuit is formed with a control area, within an address, for designating the plane on which source data should be written. A data converting circuit for writing the source data is provided in the plane of the bit map memory that is designated by data of this address control area. The write plane is designated within the address, and hence the writing on the plurality of planes can be performed at one time, thereby attaining a high-speed writing process.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: June 29, 1999
    Assignee: Fujitsu Limited
    Inventors: Seiji Inuyama, Hiroshi Onoue, Masanori Hiraoka