Abstract: A monitoring system includes an arithmetic processor. The arithmetic processor receives captured image information representing a captured image obtained by capturing an image of a subject and generates notification information representing a particular notification content depending on a condition of the subject. The arithmetic processor includes a first arithmetic processor and a second arithmetic processor. The first arithmetic processor obtains a condition quantity by quantifying the condition of the subject by reference to the captured image information and based on a parameter about a human activity status. The second arithmetic processor selects, according to the condition quantity, the particular notification content from contents of notification classified into N stages, where N is an integer equal to or greater than three.

Abstract: A monitoring system includes an arithmetic processor. The arithmetic processor receives captured image information representing a captured image obtained by capturing an image of a subject and generates notification information representing a particular notification content depending on a condition of the subject. The arithmetic processor includes a first arithmetic processor and a second arithmetic processor. The first arithmetic processor obtains a condition quantity by quantifying the condition of the subject by reference to the captured image information and based on a parameter about a human activity status. The second arithmetic processor selects, according to the condition quantity, the particular notification content from contents of notification classified into N stages, where N is an integer equal to or greater than three.

Abstract: An electrode pad is provided above a circuit block of a semiconductor integrated circuit device. A junction point A and a junction point B are provided on connection lines connecting electrode pads to an internal circuit and an electrostatic discharge (ESD) protection circuit. The junction point A and the junction point B are positioned at locations closer to the ESD protection circuit than to the electrode pads.

Abstract: An electrode pad is provided above a circuit block of a semiconductor integrated circuit device. A junction point A and a junction point B are provided on connection lines connecting electrode pads to an internal circuit and an electrostatic discharge (ESD) protection circuit. The junction point A and the junction point B are positioned at locations closer to the ESD protection circuit than to the electrode pads.

Abstract: An electrode pad is provided above a circuit block of a semiconductor integrated circuit device. A junction point A and a junction point B are provided on connection lines connecting electrode pads to an internal circuit and an electrostatic discharge (ESD) protection circuit. The junction point A and the junction point B are positioned at locations closer to the ESD protection circuit than to the electrode pads.

Abstract: Plural I/O cells (14) having electrode pads for wire bonding (13) are disposed with spaces (55) between them in the vicinity of a corner of an I/O region (11) of a semiconductor substrate (10), and power supply separation cells (16) not to be wire bonded, on which ESD (electrostatic discharge) protection circuits (4) having ESD protection transistors are amounted, are disposed between the respective I/O cells (14), whereby the chip size is reduced upon consideration of layout of the electrode pads.

Abstract: There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package.

Abstract: There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package.

Abstract: There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is made different from an arrangement order of the function terminals on the external package.

Abstract: Plural I/O cells (14) having electrode pads for wire bonding (13) are disposed with spaces (55) between them in the vicinity of a corner of an I/O region (11) of a semiconductor substrate (10), and power supply separation cells (16) not to be wire bonded, on which ESD (electrostatic discharge) protection circuits (4) having ESD protection transistors are amounted, are disposed between the respective I/O cells (14), whereby the chip size is reduced upon consideration of layout of the electrode pads.

Abstract: A power supply potential and a ground potential are supplied to a test-use power supply pad and a test-use ground pad, respectively. The power supply potential supplied to the test-use power supply pad is transferred to power supply lines and then to each circuit block via a test-use power supply line and a potential transfer circuit including a diode device. A voltage drop is caused by each of the diode devices. To cope with the voltage drop, however, respective sizes of the diode devices and resistance components of the potential transfer circuits are configured so that a uniform voltage drop is generated at each of the power supply lines.

Abstract: A power supply potential and a ground potential are supplied to a test-use power supply pad and a test-use ground pad, respectively. The power supply potential supplied to the test-use power supply pad is transferred to power supply lines and then to each circuit block via a test-use power supply line and a potential transfer circuit including a diode device. A voltage drop is caused by each of the diode devices. To cope with the voltage drop, however, respective sizes of the diode devices and resistance components of the potential transfer circuits are configured so that a uniform voltage drop is generated at each of the power supply lines.

Abstract: Each of plural semiconductor integrated circuits existing on a semiconductor wafer is provided with a function circuit (3), plural pads (4), and wirings (8) which are electrically connected to the pads (4) and contact bumps of a probe card (7), wherein at least two wirings (8a) and (8b) simultaneously contact one bump (6) in an area other than a bump area, without being in touch with each other, whereby wafer level burn-in is executed. Thereby, even when the chip area is reduced, wafer level burn-in can be carried out.

Abstract: The input/output circuit of the present invention includes a first p-channel transistor and a charge drawing circuit. The first p-channel transistor is connected to an input/output pad of the semiconductor integrated circuit. The charge drawing circuit, driven with a control signal, draws a charge from an n-well diffusion region of the p-channel transistor during output. By the charge drawing, the potential at the n-well diffusion region of the p-channel transistor is kept at the supply voltage during output, and thus the input/output circuit is prevented from deterioration in current flow capability due to a back bias effect.

Abstract: The input/output circuit of the present invention includes a first p-channel transistor and a charge drawing circuit. The first p-channel transistor is connected to an input/output pad of the semiconductor integrated circuit. The charge drawing circuit, driven with a control signal, draws a charge from an n-well diffusion region of the p-channel transistor during output. By the charge drawing, the potential at the n-well diffusion region of the p-channel transistor is kept at the supply voltage during output, and thus the input/output circuit is prevented from deterioration in current flow capability due to a back bias effect.

Abstract: The present invention attempts to speed up operations by a chien's searching apparatus used in error correction, to thereby miniaturize it and save on its power dissipation. To this end, the apparatus includes a plurality of arithmetic units which share an error-position polynomial calculating unit and an error-numeral polynomial calculating unit as well as selectors and registers, to thereby perform calculation on a plurality of orders in the same cycle. Also, a divider unit is shared in use. If no error is found, the divider unit is stopped.

Abstract: The input/output circuit of the present invention includes a first p-channel transistor and a charge drawing circuit. The first p-channel transistor is connected to an input/output pad of the semiconductor integrated circuit. The charge drawing circuit, driven with a control signal, draws a charge from an n-well diffusion region of the p-channel transistor during output. By the charge drawing, the potential at the n-well diffusion region of the p-channel transistor is kept at the supply voltage during output, and thus the input/output circuit is prevented from deterioration in current flow capability due to a back bias effect.

Abstract: The present invention attempts to speed up operations by a chien's searching apparatus used in error correction, to thereby miniaturize it and save on its power dissipation. To this end, the apparatus includes a plurality of arithmetic units which share an error-position polynomial calculating unit and an error-numeral polynomial calculating unit as well as selectors and registers, to thereby perform calculation on a plurality of orders in the same cycle. Also, a divider unit is shared in use. If no error is found, the divider unit is stopped.