Abstract: A data communication apparatus for performing communication of data with a master device via a bus includes a clock control signal generation circuit that outputs a clock control signal corresponding to a reset state and a communication state of the data communication apparatus, a communication start detection circuit that detects a start of communication on the basis of a clock signal on the bus and the data, a clock generation circuit that generates an internal clock signal on the basis of the clock signal on the bus, and a data processing control circuit that receives the internal clock signal and controls communication of the data with the master device. The clock generation circuit stops generating the internal clock signal in accordance with the clock control signal, in the reset state of the data communication apparatus and in a period from release of the reset state to the start of communication.

Abstract: A data communication apparatus for performing communication of data with a master device via a bus includes a clock control signal generation circuit that outputs a clock control signal corresponding to a reset state and a communication state of the data communication apparatus, a communication start detection circuit that detects a start of communication on the basis of a clock signal on the bus and the data, a clock generation circuit that generates an internal clock signal on the basis of the clock signal on the bus, and a data processing control circuit that receives the internal clock signal and controls communication of the data with the master device. The clock generation circuit stops generating the internal clock signal in accordance with the clock control signal, in the reset state of the data communication apparatus and in a period from release of the reset state to the start of communication.

Abstract: Provided is a data transfer device that reduces generation of noise caused by an unnecessary transfer of a serial clock signal. The data transfer device includes: a clock generator circuit that generates a second serial clock signal, the second serial clock signal being synchronized with a first serial clock signal transmitted from a master device; a determination circuit that determines whether a request from the master device is addressed to the data transfer device or not; and a data processing circuit that operates by receiving a transfer of the first serial clock signal from the clock generator circuit on condition of the request from the master device being determined to be addressed to the data transfer device.

Abstract: A register circuit for which an initial value can be changed without using a flip-flop including both a set terminal and a reset terminal is provided. The register circuit includes an initial value wiring line, a write signal terminal, a clock signal terminal, a first flip-flop, an output control circuit, a second flip-flop, and a selector.

Abstract: Provided is a data transfer device that reduces generation of noise caused by an unnecessary transfer of a serial clock signal. The data transfer device includes: a clock generator circuit that generates a second serial clock signal, the second serial clock signal being synchronized with a first serial clock signal transmitted from a master device; a determination circuit that determines whether a request from the master device is addressed to the data transfer device or not; and a data processing circuit that operates by receiving a transfer of the first serial clock signal from the clock generator circuit on condition of the request from the master device being determined to be addressed to the data transfer device.

Abstract: A register circuit for which an initial value can be changed without using a flip-flop including both a set terminal and a reset terminal is provided. The register circuit includes an initial value wiring line, a write signal terminal, a clock signal terminal, a first flip-flop, an output control circuit, a second flip-flop, and a selector.

Abstract: The invention provides a semiconductor integrated circuit device and a high-frequency power amplifier module capable of reducing variations in the transmission power characteristics. The semiconductor integrated circuit device and the high-frequency power amplifier module each include, for example, a bandgap reference circuit, a regulator circuit, and a reference-voltage correction circuit which is provided between the bandgap reference circuit and the regulator circuit and which includes a unity gain buffer. The reference-voltage correction circuit corrects variations in a bandgap voltage from the bandgap reference circuit. The reference-voltage correction circuit includes first to third resistance paths having mutually different resistance values, and corrects the variations by selectively supplying a current which reflects an output voltage of the unity gain buffer to any one of the first to third resistance paths.

Abstract: The invention provides a semiconductor integrated circuit device and a high-frequency power amplifier module capable of reducing variations in the transmission power characteristics. The semiconductor integrated circuit device and the high-frequency power amplifier module each include, for example, a bandgap reference circuit, a regulator circuit, and a reference-voltage correction circuit which is provided between the bandgap reference circuit and the regulator circuit and which includes a unity gain buffer. The reference-voltage correction circuit corrects variations in a bandgap voltage from the bandgap reference circuit. The reference-voltage correction circuit includes first to third resistance paths having mutually different resistance values, and corrects the variations by selectively supplying a current which reflects an output voltage of the unity gain buffer to any one of the first to third resistance paths.

Abstract: A switch circuit with a unit capable of improving a margin voltage without using a negative bias generation circuit is provided. A switch comprising an N-type MOSFET is used for a switch passing a signal to an antenna and a switch comprising a P-type MOSFET is used for a shunt switch grounding a signal. A common control signal is input to the gate terminal of the MOSFET constituting each switch. The inverted signal of this control signal is coupled to a ground terminal of the switch, and thus the potential of the gate terminal of each MOSFET can be set to the ground voltage.

Abstract: A radio frequency module is configured to enter a power saving mode with high reliability. The radio frequency module includes, e.g., a first switch transistor for coupling a transmission node to an antenna, a second switch transistor for shunting the transmission node to a ground voltage, and a level shift circuit for performing on-off control of the first and second switch transistors by positive and negative power supply voltages.

Abstract: To provide a fast charge means for a capacitor in a negative bias generation circuit. A capacitor is present in a down converter in a negative bias generation circuit. In order to perform fast charge, the capacitance of the capacitor is reduced and a necessary amount of charge is minimized. On the other hand, an external capacitance provided separately from the capacitor in the down converter is coupled directly to a power supply voltage and charged. After the capacitor in the down converter is charged, the external capacitance and the capacitor in the down converter are coupled in parallel. Due to this, it is made possible to aim at both the increase in charge speed and the improvement of resistance to ripple noise.

Abstract: To provide a fast charge means for a capacitor in a negative bias generation circuit. A capacitor is present in a down converter in a negative bias generation circuit. In order to perform fast charge, the capacitance of the capacitor is reduced and a necessary amount of charge is minimized. On the other hand, an external capacitance provided separately from the capacitor in the down converter is coupled directly to a power supply voltage and charged. After the capacitor in the down converter is charged, the external capacitance and the capacitor in the down converter are coupled in parallel. Due to this, it is made possible to aim at both the increase in charge speed and the improvement of resistance to ripple noise.

Abstract: To provide a fast charge means for a capacitor in a negative bias generation circuit. A capacitor is present in a down converter in a negative bias generation circuit. In order to perform fast charge, the capacitance of the capacitor is reduced and a necessary amount of charge is minimized. On the other hand, an external capacitance provided separately from the capacitor in the down converter is coupled directly to a power supply voltage and charged. After the capacitor in the down converter is charged, the external capacitance and the capacitor in the down converter are coupled in parallel. Due to this, it is made possible to aim at both the increase in charge speed and the improvement of resistance to ripple noise.

Abstract: A switch circuit with a unit capable of improving a margin voltage without using a negative bias generation circuit is provided. A switch comprising an N-type MOSFET is used for a switch passing a signal to an antenna and a switch comprising a P-type MOSFET is used for a shunt switch grounding a signal. A common control signal is input to the gate terminal of the MOSFET constituting each switch. The inverted signal of this control signal is coupled to a ground terminal of the switch, and thus the potential of the gate terminal of each MOSFET can be set to the ground voltage.

Abstract: A radio frequency module is configured to enter a power saving mode with high reliability. The radio frequency module includes, e.g., a first switch transistor for coupling a transmission node to an antenna, a second switch transistor for shunting the transmission node to a ground voltage, and a level shift circuit for performing on-off control of the first and second switch transistors by positive and negative power supply voltages.

Abstract: To provide a fast charge means for a capacitor in a negative bias generation circuit. A capacitor is present in a down converter in a negative bias generation circuit. In order to perform fast charge, the capacitance of the capacitor is reduced and a necessary amount of charge is minimized. On the other hand, an external capacitance provided separately from the capacitor in the down converter is coupled directly to a power supply voltage and charged. After the capacitor in the down converter is charged, the external capacitance and the capacitor in the down converter are coupled in parallel. Due to this, it is made possible to aim at both the increase in charge speed and the improvement of resistance to ripple noise.