Patents by Inventor Masanori Inoue

Masanori Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11945414
    Abstract: A vehicle windshield wiper blade comprising: a blade support portion; and a lip portion, wherein the lip portion has a tapered portion having a cross section that is taken along a direction perpendicular to the longitudinal direction of the wiper blade and that has a width that gradually decreases from a side closer to the blade support portion towards a direction farthest away from the blade support portion, the lip portion has a tip surface and first and second tapered surfaces constituting the tapered portion, and, in a specific observation region of the first and second tapered surfaces, the average value of the elastic modulus measured at a 0.1 ?m pitch is 15-470 MPa and the coefficient of variation of the elastic modulus is at most 17.6%.
    Type: Grant
    Filed: January 24, 2023
    Date of Patent: April 2, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takehiko Aoyama, Masanori Yokoyama, Syoji Inoue, Arihiro Yamamoto, Hidekazu Matsuda, Shota Segawa
  • Publication number: 20230325596
    Abstract: In an information processing apparatus (10), a communication unit (11) receives a text created in a terminal device (20), and a control unit (13) performs noise detection to determine whether a noise expression is included in the received text and notifies, when the noise expression is included in the received text, the terminal device (20) of detection of the noise expression.
    Type: Application
    Filed: September 17, 2021
    Publication date: October 12, 2023
    Applicant: Sony Group Corporation
    Inventors: Chiaki HIGASHINAKA, Saya SUZUKI, Remu HIDA, Masanori INOUE
  • Publication number: 20220238109
    Abstract: An information processor according to the present disclosure includes an acquisition unit that acquires first information serving as a trigger for interaction, second information indicating an answer to the first information, and third information indicating a response to the second information; and a collection unit that collects a combination of the first information, the second information, and the third information acquired by the acquisition unit.
    Type: Application
    Filed: April 30, 2020
    Publication date: July 28, 2022
    Applicant: Sony Group Corporation
    Inventors: Remu HIDA, Saya KANNO, Chiaki MIYAZAKI, Masanori INOUE
  • Publication number: 20220140082
    Abstract: Provided is a semiconductor apparatus comprising: a semiconductor substrate; an element electrode provided above the semiconductor substrate; an element electrode pad electrically connected to the element electrode; and a wire configured to connect to the element electrode pad at a plurality of connection points, wherein the semiconductor substrate includes an emitter region of a first conductivity type arrayed in an array direction, the emitter region facing the element electrode on an upper surface of the semiconductor substrate, wherein a density of the emitter region below a connection point of any of the wires is different from a density of the emitter region below a connection point of any other of the wires.
    Type: Application
    Filed: September 28, 2021
    Publication date: May 5, 2022
    Inventor: Masanori INOUE
  • Patent number: 11223158
    Abstract: This disclosure provides a waterproof electronic component having good waterproofness and a method for assembling the waterproof electronic component. A repeater as a waterproof electronic component includes (i) a substrate having first through holes, (ii) a socket fixed to the substrate, (iii) a housing containing the substrate, (iv) a pin held by the housing and having a first end connected to the substrate, and (v) a sealing section with which an area surrounded by the substrate and the housing is filled, the housing including a support including a supportive wall section capable of supporting a fixation portion of the socket and a seat section having a seating surface on which the substrate is placed, the substrate being placed on the seat section, the socket being oriented in such a manner that at least a portion of an outer surface of the fixation portion is close to and faces the supportive wall section.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: January 11, 2022
    Assignee: Hosiden Corporation
    Inventors: Satoshi Yamanaka, Masanori Inoue
  • Publication number: 20210006005
    Abstract: This disclosure provides a waterproof electronic component having good waterproofness and a method for assembling the waterproof electronic component. A repeater as a waterproof electronic component includes (i) a substrate having first through holes, (ii) a socket fixed to the substrate, (iii) a housing containing the substrate, (iv) a pin held by the housing and having a first end connected to the substrate, and (v) a sealing section with which an area surrounded by the substrate and the housing is filled, the housing including a support including a supportive wall section capable of supporting a fixation portion of the socket and a seat section having a seating surface on which the substrate is placed, the substrate being placed on the seat section, the socket being oriented in such a manner that at least a portion of an outer surface of the fixation portion is close to and faces the supportive wall section.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 7, 2021
    Inventors: Satoshi YAMANAKA, Masanori INOUE
  • Patent number: 10164058
    Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: December 25, 2018
    Assignees: FUJI ELECTRIC CO., LTD., Japan Aerospace Exploration Agency
    Inventors: Shuhei Tatemichi, Shunji Takenoiri, Masanori Inoue, Yuji Kumagai, Satoshi Kuboyama, Eiichi Mizuta
  • Patent number: 10085237
    Abstract: The invention relates to an information processing device, wireless communication system, and information processing method to establish stable wireless communication with a terminal. The information processing device includes a frequency identifying unit configured to identify a frequency used for wireless communication between another information processing device and an access point on the basis of communication, and a communication control unit configured to use the acquired frequency to establish wireless communication with the other information processing device.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: September 25, 2018
    Assignee: SONY CORPORATION
    Inventors: Toru Nagara, Masanori Inoue
  • Patent number: 9842912
    Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: December 12, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shuhei Tatemichi, Shunji Takenoiri, Masanori Inoue, Yuji Kumagai, Satoshi Kuboyama, Eiichi Mizuta
  • Publication number: 20170301764
    Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 19, 2017
    Inventors: Shuhei TATEMICHI, Shunji TAKENOIRI, Masanori INOUE, Yuji KUMAGAI, Satoshi KUBOYAMA, Eiichi MIZUTA
  • Patent number: 9704946
    Abstract: A semiconductor device is provided. On one main surface side of an n-type semiconductor substrate, a p-type diffusion region to serve as an anode of a diode is formed. A guard ring formed of a p-type diffusion region is formed to surround the anode. On the other main surface side, an n-type ultrahigh-concentration impurity layer and an n-type high-concentration impurity layer to serve as a cathode are formed. In a guard-ring opposed region located in the cathode and opposite to the guard ring, a cathode-side p-type diffusion region is formed. Accordingly, concentration of the electric current on an outer peripheral end portion of the anode is suppressed.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: July 11, 2017
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro Yoshiura, Masanori Inoue
  • Patent number: 9608057
    Abstract: A MOS semiconductor device has a MOS structure, including a p? region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n? layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 28, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shuhei Tatemichi, Takeyoshi Nishimura, Yasushi Niimura, Masanori Inoue
  • Patent number: 9608625
    Abstract: According to one embodiment, a semiconductor device includes: a voltage line to which a first voltage is applied; a first circuit configured to operate by using the first voltage; and a second circuit configured to control a connection between the voltage line and the first circuit. The second circuit includes: at least one first switch circuit configured to connect the first circuit and the voltage line based on a first control signal; and a second switch circuit including a plurality of switch sections configured to connect the first circuit and the voltage line based on a plurality of second control signals different from the first control signal.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: March 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Kunie, Masanori Inoue
  • Publication number: 20170054000
    Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.
    Type: Application
    Filed: June 10, 2016
    Publication date: February 23, 2017
    Inventors: Shuhei TATEMICHI, Shunji TAKENOIRI, Masanori INOUE, Yuji KUMAGAI
  • Publication number: 20160197140
    Abstract: A MOS semiconductor device has a MOS structure, including a p? region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n? layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.
    Type: Application
    Filed: March 11, 2016
    Publication date: July 7, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Shuhei TATEMICHI, Takeyoshi NISHIMURA, Yasushi NIIMURA, Masanori INOUE
  • Publication number: 20160182041
    Abstract: According to one embodiment, a semiconductor device includes: a voltage line to which a first voltage is applied; a first circuit configured to operate by using the first voltage; and a second circuit configured to control a connection between the voltage line and the first circuit. The second circuit includes: at least one first switch circuit configured to connect the first circuit and the voltage line based on a first control signal; and a second switch circuit including a plurality of switch sections configured to connect the first circuit and the voltage line based on a plurality of second control signals different from the first control signal.
    Type: Application
    Filed: September 3, 2015
    Publication date: June 23, 2016
    Inventors: Shuichi Kunie, Masanori Inoue
  • Patent number: 9331194
    Abstract: A MOS semiconductor device has a MOS structure, including a p? region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n? layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: May 3, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shuhei Tatemichi, Takeyoshi Nishimura, Yasushi Niimura, Masanori Inoue
  • Publication number: 20160073377
    Abstract: [Object] To provide a novel and improved information processing device, wireless communication system, and information processing method that can establish stable wireless communication with a terminal without a complicated procedure. [Solution] There is provided an information processing device including a frequency identifying unit configured to identify a frequency used for wireless communication between another information processing device and an access point on the basis of communication, and a communication control unit configured to use the acquired frequency to establish wireless communication with the other information processing device.
    Type: Application
    Filed: February 24, 2014
    Publication date: March 10, 2016
    Inventors: Toru NAGARA, Masanori INOUE
  • Patent number: 9123767
    Abstract: An MOS semiconductor device including an MOS gate structure is disclosed. The MOS semiconductor device includes a p-type well region selectively disposed on the surface layer of an n-type drift layer formed on a semiconductor substrate forming an n-type drain region; an n-type source region selectively disposed on the surface layer of the p-type well region; and a gate electrode placed, via an insulating film, on the surface of a channel formation region on the surface layer of the p-type well region sandwiched between the n-type source region and the surface layer of the n-type drain region, wherein a surface in the channel formation region has a level difference formed in the direction of the peripheral length, and all over the length, of the channel formation region.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: September 1, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masanori Inoue
  • Patent number: D945969
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: March 15, 2022
    Assignee: Hosiden Corporation
    Inventors: Satoshi Yamanaka, Masanori Inoue