Abstract: A charge pump circuit includes a charge pump which includes a first series connection of at least a first conductivity type field effect transistor between a high voltage line and an intermediate point connected to an output terminal; and a second series connection of at least a second conductivity type field effect transistor between a low voltage line and the intermediate point; a replica circuit which includes a third series connection of at least a first conductivity type field effect transistor between the high voltage line and the intermediate point; and a fourth series connection of at least a second conductivity type field effect transistor between the low voltage line and the intermediate point, the replica circuit has substantially the same circuit configuration and characteristics as the charge pump; and a control circuit connected to the charge pump and the replica circuit for controlling the charge pump and the replica circuit, so that an output voltage level of the replica circuit is equal to an

Abstract: Data is asynchronously transferred between a semiconductor static random access memory device and an external device equipped with an asynchronous access controller by using an access request signal representative of a request for accessing data bits stored in the semiconductor static random access memory device and an acknowledge signal representative of completion of the data access, and Muller's c-elements are incorporated in the asynchronous access controller for producing the access request signal at more than one timing in each access cycle under the control of two clock signals different in phase from each other.

Abstract: A digital phase locked loop (PLL) comprises a phase/frequency comparator block including a comparator for comparing a reference signal with an internal clock signal obtained by dividing an output clock signal of the PLL circuit. The phase/frequency comparator supplies a two-bit signal, either one of the bits having a pulse width based on the difference between the phases or frequencies of the reference signal and internal clock signal. The two-bit signal is amplified by a CMOS latch amplifier during a sense enable cycle of the amplifier to be supplied to a digital controller, which in turn controls a voltage controlled oscillator via a D/A converter. The digital PLL circuit executes frequency acquisition and phase acquisition in a single mode to simplify the circuit configuration.

Abstract: A voltage controlled oscillator circuit comprises a first lowpass OTA-C filter with differential input and differential output and a second lowpass OTA-C filter with differential input and differential output. A non-inverted output terminal of the first OTA-C filter is connected with a non-inverted input terminal of the second OTA-C filter, an inverted output terminal of the first OTA-C filter is connected with an inverted input terminal of the second OTA-C filter, a non-inverted output terminal of the second OTA-C filter is connected with an inverted input terminal of the first OTA-C filter, and an inverted output terminal of the second OTA-C filter is connected with a non-inverted input terminal of the first OTA-C filter. Gate widths of input terminals of OTAs in each OTA-C filter are set appropriately, and initial values of terminals are set by nMOSFETs 3-6, and oscillation output is outputted from the non-inverted output terminal and the inverted output terminal of the second OTA-C filter.

Abstract: A D/A converter implemented by an integrated circuit has a first section for conversion of higher-order N1 bits of an input digital signal to output a first current signal I.sub.1, a second section for conversion of lower-order N2 bits of the input digital signal to output a second current signal I.sub.2, a dividing section for dividing the second current signal to output a third current signal I.sub.2 .times.1/2.sup.N2, and an adding section for adding the first and third current signal. The D/A converter can be implemented by a reduced number of MOSFETs and has a reduced occupied area.