Abstract: Disclosed is a non-volatile semiconductor memory apparatus, having floating gate electrodes, from which multi-value data can be accurately read out. A memory cell transistor (40) is provided in a row with a plurality of reference transistors (50), and a plurality of such rows are selectively connected by a word line (43). Reference potentials (Va˜Vc) are written to the reference transistors (50) simultaneous to the writing of data to the memory cell transistor (40). In read mode, following the completion of the writing operation, memory data is determined by comparing reference potentials (VR1˜VR3) which have been read out from the reference transistors (50), with a potential (VBL) which has been read out from the memory cell transistor (40).

Abstract: A semiconductor memory device is described that has an improved read characteristics. The semiconductor memory device includes a plurality of memory cells, a reference cell, a comparator located between the memory cells and the reference cell, and a discriminator coupled to the comparator. The comparator compares the actual signal equivalent to a value of a current flowing in each of the memory cells and reference signals equivalent to a value of a current flowing in the reference cell with each other to output a comparison result signal in each of data reading operation modes. The discriminator discriminates a value of data stored in each of the memory cells based on the comparison result signal. The discriminator includes a circuit shared for discrimination of a data value in each of the data reading operation modes.

Abstract: In order to increase the efficiency of a write operation with respect to a non-volatile semiconductor memory having a floating gate electrode, a memory cell transistor (40) is connected to a bit line (42), which is further connected to a current limitation circuit (30). The current limitation circuit (30) comprises a number of parallely connected switching transistors (31 to 34), and grounds the bit line (42). While a constant level for a write clock .phi.W supplied via a bit line 42, remains, the switching transistors (31 to 34) are stepwise turned to thereby stepwise increase a write current IPP, allowing analog information to be written into the memory cell transistor (40).

Abstract: A digital/analog converter of the present invention is a pulse width modulation type, and is provided with a 2.sup.N (N: the number of bits of digital data to be converted) notation counter circuit for counting clock pulses, pulse formation circuit which is given the counting output of the counter circuit and the digital data and outputs a pulse signal being varied its pulse width and pulse cycle period corresponding to the contents of the digital data and being decided the sum of the pulse widths of the pulse signal in the 2.sup.N clocks period corresponding to the same, and means which selects corresponding to the pulse one of two potentials different in level and which composed the selected potential, so that the harmonic spectrum of an analog signal obtained as the output of the composite means is larger in the high band and smaller in the low band, resulting in that the digital/analog converter less in the harmonic distortion without using resistance of high accuracy is obtainable.