Patents by Inventor Masanori Kinugasa
Masanori Kinugasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6169443Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.Type: GrantFiled: November 9, 1999Date of Patent: January 2, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa, Toshinobu Hisamoto
-
Patent number: 6097217Abstract: Either the power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to an output terminal while the power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to a pn-junction provided between the drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.Type: GrantFiled: December 14, 1998Date of Patent: August 1, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
-
Patent number: 6054736Abstract: A semiconductor device of the present invention comprises: a semiconductor substrate of a first conductive type; a gate electrode formed on the semiconductor substrate; a first semiconductor region of a second conductive type different from the first conductive type, the first semiconductor region being formed on the semiconductor substrate in one of both side regions of the gate electrode so as to be adjacent to the gate electrode; a second semiconductor region of the second conductive type formed on the semiconductor substrate in the other region of the both side regions of the gate electrode so as to be adjacent to the gate electrode; a third semiconductor region of the second conductive type formed in the one region so as to be isolated from the first semiconductor region and to be spaced from the second semiconductor region by a greater distance than that between the first and third semiconductor regions; a connecting portion for connecting the first semiconductor region to the third semiconductor regionType: GrantFiled: May 13, 1998Date of Patent: April 25, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa, Akira Takiba, Ryouichi Isohata
-
Patent number: 6020778Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.Type: GrantFiled: April 23, 1998Date of Patent: February 1, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa, Toshinobu Hisamoto
-
Patent number: 5892387Abstract: In a situation where another analog switching circuit 502 outputs a high potential Vh, this high potential Vh is applied to an output terminal OUT1 of an analog switching circuit 504. When a ground potential is supplied to a node 10 with a changeover switch SW, a diode DD1 falls to an inversely biased state, whereby a potential at a backgate node Nw comes to be approximately equal to the potential Vh. Moreover, a potential approximately equal to the potential Vh is a power source terminal of an NAND gate NAND1, and it is transmitted to an output terminal VGP through an internal circuit, whereby a P channel MOS transistor P1 is turned off. Moreover, the output VGP from an inverter INV5 makes also an N channel MOS transistor N1 turn off. With such a constitution, an unnecessary current is prevented from flowing from a power source potential terminal on a bus line and so on to a ground potential terminal through a parasitic diode, thereby performing full-swinging without lowering an output level.Type: GrantFiled: July 15, 1997Date of Patent: April 6, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
-
Patent number: 5880603Abstract: Either a power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to an output terminal while the power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to a pn-junction provided between the drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.Type: GrantFiled: May 31, 1996Date of Patent: March 9, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
-
Patent number: 5831449Abstract: An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.Type: GrantFiled: April 21, 1997Date of Patent: November 3, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
-
Patent number: 5825220Abstract: An auto-clear circuit which has a switch device connected between a power supply voltage terminal and first and second nodes, and a potential division device, connected between the first node and a ground terminal, for outputting a first potential obtained by dividing a potential of the first node. Also included is a charge/discharge device, connected between the second node and a ground terminal, for charging or discharging the second node on the basis of the first potential output from the potential division device, and a latch device for holding a potential of the second node to output a signal from an output terminal, and supplying the signal to the switch device to control an opening/closing operation.Type: GrantFiled: January 2, 1997Date of Patent: October 20, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Masanori Kinugasa, Hiroshi Shigehara, Akira Takiba
-
Patent number: 5821797Abstract: A protection circuit (1) for input comprises two transistors (11, 12) connected in series between a first voltage supply (V.sub.cc) and a second voltage supply (GND), and an intermediate junction point is used as an input terminal and an output terminal. When a surge voltage is applied to the input terminal, since terminals (51, 53) of the two transistors (11, 12) are connected to predetermined junction points in such a way that the transistors can operate as bipolar transistors or cause punch through phenomenon (without causing breakdown operation of a low response speed to surge voltage), the surge voltage can be absorbed at high speed, thus increasing anti-ESD (electro static discharge) rate. Further, a protection circuit for power supply comprises two transistors (31, 32) connected in parallel to each other between a first voltage supply (V.sub.cc) and a second voltage supply (GND).Type: GrantFiled: March 29, 1996Date of Patent: October 13, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Masanori Kinugasa, Ryuji Fujiwara
-
Patent number: 5739702Abstract: The bus hold circuit comprises: an input stage inverter (IN1) connected between a first supply voltage (Vcc) terminal and a second supply voltage (Vss) terminal and including: a first P-channel transistor (P1); and a first N-channel transistor (N1) connected in series to the first P-channel transistor, a gate of the first P-channel transistor and a gate of the first N-channel transistor being connected in common to a bus line (INA); and an output stage inverter (IN2) also connected between the first supply voltage (Vcc) terminal and the second supply voltage (Vss) terminal and including: a second P-channel transistor (P4); a third P-channel transistor (P2) connected in series to the second P-channel transistor; and a second N-channel transistor (N2) connected in series to the third P-channel transistor, a gate of the second P-channel transistor (P4) being connected to the bus line (Lout), a gate of the third P-channel transistor (P2) and a gate of the second N-channel transistor (N2) being connected in commonType: GrantFiled: August 29, 1996Date of Patent: April 14, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
-
Patent number: 5661414Abstract: An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the Gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.Type: GrantFiled: February 15, 1995Date of Patent: August 26, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
-
Patent number: 5552723Abstract: An output circuit according to the present invention comprises an input terminal, first and second MOS transistors of a same conductivity type connected in series between first and second power supplies to form a current path, and alternately turned on in response to an input signal from the input terminal, an output terminal connected to a connection point of the current path of the first and second MOS transistors, and a switching element having a current path one end of which is connected to the output terminal and another end of which is connected to a back gate of the first MOS transistor, for performing a switching operation in response to the input signal from the input terminal, the switching element preventing a parasitic diode generated between the back gate of the first MOS transistor and the first power supply from turning on, and controlling a potential of the back gate of the first MOS transistor.Type: GrantFiled: June 23, 1994Date of Patent: September 3, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
-
Patent number: 5539327Abstract: A transistor circuit comprises a MOS transistor with an open back gate, and control means for controlling a voltage to be applied to the control gate of the MOS transistor, whereby the control means controls the avalanche breakdown voltage of a parasitic bipolar transistor formed by the drain, back gate and source of the MOS transistor.Type: GrantFiled: December 2, 1994Date of Patent: July 23, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
-
Patent number: 5493233Abstract: A transistor circuit apparatus comprises a MOS transistor to be improved, for preventing an avalanche breakdown, the MOS transistor being connected in a channel conductor path provided between one of power supply terminals and a terminal of an output, a separate circuit connected to the output terminal and driven by a voltage from a separate power supply, and a pull-down unit including a second transistor connected between one of said power supply terminals and a back gate of the MOS transistor, the second transistor being turned on with an output node of the separate circuit used as power supply when the MOS transistor remains at a ground potential level with no power supply potential supplied, thereby pulling down the potential level of a back gate node of the MOS transistor to the level of one of the power supply terminals.Type: GrantFiled: December 2, 1994Date of Patent: February 20, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
-
Patent number: 5445806Abstract: A process for preparing a fine powder of perovskite-type compounds having an average particle size of at most 0.3 .mu.Type: GrantFiled: March 4, 1992Date of Patent: August 29, 1995Assignee: Tayca CorporationInventors: Masanori Kinugasa, Naoto Tsubomoto, Osamu Kobayashi
-
Patent number: 5442307Abstract: An interface circuit includes first and second MOS transistors of depletion type, first and second switching elements, and a control circuit. The current path of the first MOS transistor is connected between an output node of a MOS circuit formed in a semiconductor substrate and an output terminal and the gate thereof is connected to a power supply. The first switching element is connected between the backgate of the first MOS transistor and a ground terminal. The second switching element and the current path of the second MOS transistor are serially connected between the backgate of the first MOS transistor and the output terminal. The gate of the second MOS transistor is connected to the power supply and the backgate thereof is connected to the backgate of the first MOS transistor. The first and second switching elements are set into complementary states according to an output of the MOS circuit in response to an output signal of the control circuit.Type: GrantFiled: April 12, 1994Date of Patent: August 15, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
-
Patent number: 5402005Abstract: At least one slit having a predetermined shape is formed around a contact region of a lower wiring layer formed on a substrate, and an insulating portion formed integrally with an insulating layer is embedded in this slit. This insulating layer is formed on the lower wiring layer and has a contact hole located at a position corresponding to the contact region. Since the insulating portion as a rectangular projecting portion projects into the slit downwardly from the rigid insulating layer, positional errors caused by thermal expansion of the lower wiring layer in annealing of the upper wiring layer can be suppressed, and an abnormal geometry such as a projection on the upper wiring layer can be prevented. In addition, a semiconductor device free from interwiring short-circuiting and excellent in flatness can be obtained.Type: GrantFiled: August 15, 1994Date of Patent: March 28, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Kohichi Takayama, Masanori Kinugasa, Munenobu Kida, Shuichi Shoji
-
Patent number: 5389834Abstract: This invention discloses a signal output circuit including DC and AC buffers having output nodes commonly connected to a signal output terminal, and an AC buffer control circuit for driving the AC buffer when an output from the DC buffer is changed and for controlling an output from the AC buffer in a high-impedance state when the output from the DC buffer is stationary.Type: GrantFiled: November 12, 1992Date of Patent: February 14, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Masanori Kinugasa, Satoshi Nonaka, Hiroshi Shigehara
-
Patent number: 5382846Abstract: The source-drain paths of first and second N-channel MOS transistors are series-connected between a first node to which a first power source voltage is applied and a second node to which a ground voltage is applied. The gate of the first MOS transistor is supplied with an input signal and the gate of the second MOS transistor is supplied with a signal obtained by inverting the input signal by means of a CMOS inverter. The inverter is supplied with a second power source voltage which is independent from the first power source voltage as an operation power source voltage.Type: GrantFiled: December 10, 1992Date of Patent: January 17, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
-
Patent number: 5321326Abstract: An output buffer circuit includes a first output buffer having a high output resistance determined by DC specifications, a second output buffer having an output resistance satisfying AC specifications when simultaneously driven with the first output buffer, and a control circuit for controlling an operation of the second output buffer. An input signal is supplied to the input node of the first output buffer, and the output node of the first output buffer is connected to an output terminal. The output node of the second output buffer is connected to the output terminal. The control circuit is responsive to the potential of the input signal or of the output terminal to control the operation of the second output buffer. The control circuit drives the second output buffer when the output from the first output buffer is changed, and sets the output from the second output buffer in the high impedance state when the output from the first output buffer is stationary.Type: GrantFiled: April 29, 1992Date of Patent: June 14, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa