Patents by Inventor Masanori Kurimoto
Masanori Kurimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11390290Abstract: The vehicle electronic control apparatus includes two or more FPGAs that each receive information from the sensor, a nonvolatile memory that holds a bit stream for determining a configuration for the FPGA, an MCU that incorporates two or more nonvolatile memories, in each of which a program code for calculating the control command is installed, and an error control module that outputs an error signal to the outside at a time when an abnormality occurs in at least one of the FPGA and the nonvolatile memory incorporated in the MCU; the nonvolatile memory that holds the bit stream and the nonvolatile memory incorporated in the MCU can be accessed from the outside.Type: GrantFiled: February 26, 2019Date of Patent: July 19, 2022Assignee: Mitsubishi Electric CorporationInventor: Masanori Kurimoto
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Publication number: 20200001885Abstract: The vehicle electronic control apparatus includes two or more FPGAs that each receive information from the sensor, a nonvolatile memory that holds a bit stream for determining a configuration for the FPGA, an MCU that incorporates two or more nonvolatile memories, in each of which a program code for calculating the control command is installed, and an error control module that outputs an error signal to the outside at a time when an abnormality occurs in at least one of the FPGA and the nonvolatile memory incorporated in the MCU; the nonvolatile memory that holds the bit stream and the nonvolatile memory incorporated in the MCU can be accessed from the outside.Type: ApplicationFiled: February 26, 2019Publication date: January 2, 2020Applicant: Mitsubishi Electric CorporationInventor: Masanori KURIMOTO
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Patent number: 10447223Abstract: Provided is a gain control amplification device having a wide range and high accuracy and configured to adapt measurement target current to the input range of an A/D converter. The gain control amplification device includes: a plurality of differential amplifiers having different gains with respect to measurement target current or voltage; a threshold control circuit for comparing output of the differential amplifier with threshold voltage; a switch for selecting output of one of the plurality of differential amplifiers on the basis of output of the threshold control circuit; and an offset control circuit OF and an addition circuit for adding offset voltage to output of one of the differential amplifiers.Type: GrantFiled: December 7, 2017Date of Patent: October 15, 2019Assignee: Mitsubishi Electric CorporationInventors: Masanori Kurimoto, Yuki Iwagami, Masamitsu Uchiyama
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Patent number: 10416220Abstract: Even when parts having individual differences among identical parts or differences in deterioration speed between parts, or a part that does not have a non-volatile memory such as an EEPROM in a chip of the part itself, are mixed, there is no deterioration diagnosis device that can appropriately diagnose a state of deterioration due to temporal change or the like, because of which a mechanism (correction methodology) for evaluating and correcting deterioration in the precision or performance of an electronic part that has low precision or considerable temporal deterioration, and does not have a correction function, is incorporated in a deterioration diagnosis device, and a deterioration state is diagnosed using incorporated deterioration determination means when using a product after shipping.Type: GrantFiled: February 3, 2017Date of Patent: September 17, 2019Assignee: Mitsubishi Electric CorporationInventors: Masanori Kurimoto, Yuki Iwagami, Yoshitake Nishiuma, Takayuki Yanai
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Publication number: 20180358944Abstract: Provided is a gain control amplification device having a wide range and high accuracy and configured to adapt measurement target current to the input range of an A/D converter. The gain control amplification device includes: a plurality of differential amplifiers having different gains with respect to measurement target current or voltage; a threshold control circuit for comparing output of the differential amplifier with threshold voltage ; a switch for selecting output of one of the plurality of differential amplifiers on the basis of output of the threshold control circuit ; and an offset control circuit OF and an addition circuit for adding offset voltage to output of one of the differential amplifiers.Type: ApplicationFiled: December 7, 2017Publication date: December 13, 2018Applicant: Mitsubishi Electric CorporationInventors: Masanori KURIMOTO, Yuki IWAGAMI, Masamitsu UCHIYAMA
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Publication number: 20170356947Abstract: Even when parts having individual differences among identical parts or differences in deterioration speed between parts, or a part that does not have a non-volatile memory such as an EEPROM in a chip of the part itself, are mixed, there is no deterioration diagnosis device that can appropriately diagnose a state of deterioration due to temporal change or the like, because of which a mechanism (correction methodology) for evaluating and correcting deterioration in the precision or performance of an electronic part that has low precision or considerable temporal deterioration, and does not have a correction function, is incorporated in a deterioration diagnosis device, and a deterioration state is diagnosed using incorporated deterioration determination means when using a product after shipping.Type: ApplicationFiled: February 3, 2017Publication date: December 14, 2017Applicant: Mitsubishi Electric CorporationInventors: Masanori KURIMOTO, Yuki IWAGAMI, Yoshitake NISHIUMA, Takayuki YANAI
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Patent number: 9707908Abstract: A driving device 5 includes: a fault detection device 11 that determines a fault in an actuator 6; a serial interface 7 that communicates with an MCU 2; a memory device 10 that stores a program received from the MCU 2 and a fault determination result by the fault detection device 11; a CPU 9 that causes the fault detection device 11 to execute the fault determination according to a fault determination request from the MCU 2; a timer device 16 that measures a limit time over which fault determination is performed and a determination period of fault determination; and a counter device 17 that counts the number of repeats of fault determination and the number of fault occurrences in the actuator 6.Type: GrantFiled: February 16, 2016Date of Patent: July 18, 2017Assignee: Mitsubishi Electric CorporationInventors: Masanori Kurimoto, Yuki Iwagami
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Publication number: 20170021782Abstract: A driving device 5 includes: a fault detection device 11 that determines a fault in an actuator 6; a serial interface 7 that communicates with an MCU 2; a memory device 10 that stores a program received from the MCU 2 and a fault determination result by the fault detection device 11; a CPU 9 that causes the fault detection device 11 to execute the fault determination according to a fault determination request from the MCU 2; a timer device 16 that measures a limit time over which fault determination is performed and a determination period of fault determination; and a counter device 17 that counts the number of repeats of fault determination and the number of fault occurrences in the actuator 6.Type: ApplicationFiled: February 16, 2016Publication date: January 26, 2017Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Masanori KURIMOTO, Yuki IWAGAMI
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Publication number: 20120005641Abstract: The present invention provides a semiconductor designing apparatus realizing dispersed power consumption timings without causing a setup violation and a hold violation. An STA unit calculates a setup slack as a margin of setup time of a flip-flop on the basis of a present design value of a clock latency of the flip-flop. Based on the calculated setup slack, an HSLD unit adjusts the clock latency of the flip-flop so as to be advanced more than a present design value without causing a timing violation. When a peak equal to or larger than a threshold value remains in the number of synchs in a clock latency distribution as a result of the latency control of the HSLD unit, a PAS unit smoothes the clock latency of the flip-flop without causing a timing violation on the basis of the timing information recalculated by the HSLD unit.Type: ApplicationFiled: June 22, 2011Publication date: January 5, 2012Inventors: Masanori KURIMOTO, Takashi Tsukamoto, Yoshio Inoue
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Publication number: 20110296260Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.Type: ApplicationFiled: August 9, 2011Publication date: December 1, 2011Applicant: Renesas Electronics CorporationInventor: Masanori KURIMOTO
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Patent number: 8028210Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.Type: GrantFiled: February 14, 2011Date of Patent: September 27, 2011Assignee: Renesas Electronics CorporationInventor: Masanori Kurimoto
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Publication number: 20110138217Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.Type: ApplicationFiled: February 14, 2011Publication date: June 9, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Masanori KURIMOTO
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Patent number: 7913139Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.Type: GrantFiled: October 7, 2010Date of Patent: March 22, 2011Assignee: Renesas Electronics CorporationInventor: Masanori Kurimoto
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Publication number: 20110029829Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.Type: ApplicationFiled: October 7, 2010Publication date: February 3, 2011Applicant: RENESAS TECHNOLOGY CORP.Inventor: Masanori KURIMOTO
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Patent number: 7827454Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.Type: GrantFiled: July 11, 2008Date of Patent: November 2, 2010Assignee: Renesas Electronics CorporationInventor: Masanori Kurimoto
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Publication number: 20090024888Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.Type: ApplicationFiled: July 11, 2008Publication date: January 22, 2009Inventor: Masanori KURIMOTO
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Patent number: 6978429Abstract: A logic simulation apparatus is provided with a circuit dividing unit (6) that selects and defines logic cones each of which carries out a logic operation in synchronization with one clock domain as target portions to be speeded up from logic cones extracted by a logic cone extracting unit (5), and that defines logic cones each of which carries out a logic operation based on a plurality of clock domains as nontarget portions not to be speeded up, and a logic compressing unit (7) that compresses the logic of each of the target portions, and performs a logic simulation on each of the target portions whose logic is compressed and also on performs a logic simulation on each of the nontarget portions.Type: GrantFiled: November 5, 2003Date of Patent: December 20, 2005Assignee: Renesas Technology Corp.Inventors: Akira Yoshida, Masanori Kurimoto
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Patent number: 6789055Abstract: The outputting of an output pulse produced in response to the inputting of a data pulse and a clock pulse to a D type flip-flop circuit is repeatedly simulated in a simulation process to extract a pulse time difference between the data pulse and the clock pulse as a timing verification checking value in a checking value extracting process on condition that the level of the output pulse becomes higher than a reference voltage until a simulation completion time and the pulse time difference is within a prescribed range. After the first simulation, an optimum simulation completion time, at which the levels of the data pulse, the clock pulse and the output pulse are respectively set to a constant high value, is determined to be place the optimum simulation completion time between a simulation start time and the simulation completion time, and the level of the output pulse is checked at the optimum simulation completion time in simulations following the first simulation.Type: GrantFiled: November 7, 2000Date of Patent: September 7, 2004Assignee: Renesas Technology Corp.Inventors: Shigeru Kuriyama, Masahiko Oomura, Chie Hiramine, Hiromi Fujita, Masanori Kurimoto, Takeshi Shibagaki
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Publication number: 20040107086Abstract: A logic simulation apparatus is provided with a circuit dividing unit (6) that selects and defines logic cones each of which carries out a logic operation in synchronization with one clock domain as target portions to be speeded up from logic cones extracted by a logic cone extracting unit (5), and that defines logic cons each of which carries out a logic operation based on a plurality of clock domains as nontarget portions not to be speeded up, and a logic compressing unit (7) that compresses the logic of each of the target portions, and performs a logic simulation on each of the target portions whose logic is compressed and also on performs a logic simulation on each of the nontarget portions.Type: ApplicationFiled: November 5, 2003Publication date: June 3, 2004Applicant: Renesas Technology Corp.Inventors: Akira Yoshida, Masanori Kurimoto