Abstract: Disclosed aspects relate to hardware-based memory protection of a container-based virtualization environment. A set of access identifiers for a container of a kernel process related to a memory component may be established. An access request from a first user process to a first portion of the memory component may be received. A first candidate access identifier for the first portion of the memory component may be detected. A first access identifier of the set of access identifiers that corresponds to the first portion of the memory component may be identified. A hardware-based memory protection response operation may be determined. The hardware-based memory protection response operation may be carried-out.

Abstract: Disclosed aspects relate to hardware-based memory protection of a container-based virtualization environment. A set of access identifiers for a container of a kernel process related to a memory component may be established. An access request from a first user process to a first portion of the memory component may be received. A first candidate access identifier for the first portion of the memory component may be detected. A first access identifier of the set of access identifiers that corresponds to the first portion of the memory component may be identified. A hardware-based memory protection response operation may be determined. The hardware-based memory protection response operation may be carried-out.

Abstract: In an environment in which a processor operates a hypervisor and multiple guest partitions operating under the hypervisor's control, it is desirable to allow a guest partition access to a physical memory device without decreasing system performance. Accordingly, a conversion instruction for converting a logical address to a real address, i.e., an LTOR instruction, executable from a guest partition, is added to the processor. Upon the guest partition's execution of the conversion instruction with the logical address specified, the processor converts the logical address to an encrypted real address, and returns it to the guest partition. The guest partition is then able to pass the encrypted real address to an accelerator that converts the encrypted real address to a real address in order to access the memory device using the real address.

Abstract: A technique for register mapping in a virtual system includes preparing a register pool that includes a plurality of registers for mapping. A mapping table is prepared that has a register identifier (ID) and information related to each of a plurality of parameters that express an operational state of the virtual system for each of the registers. At the time a register access request is issued by a hardware thread, the register ID for an access target and information related to each of the plurality of parameters that express the operational state during operation is acquired. One of the registers, for which the acquired register ID and information related to each of the plurality of parameters match the register ID and information for each of the plurality of parameters within the mapping table, is set as a mapped register to be accessed per the register access request.

Abstract: A technique for register mapping in a virtual system includes preparing a register pool that includes a plurality of registers for mapping. A mapping table is prepared that has a register identifier (ID) and information related to each of a plurality of parameters that express an operational state of the virtual system for each of the registers. At the time a register access request is issued by a hardware thread, the register ID for an access target and information related to each of the plurality of parameters that express the operational state during operation is acquired. One of the registers, for which the acquired register ID and information related to each of the plurality of parameters match the register ID and information for each of the plurality of parameters within the mapping table, is set as a mapped register to be accessed per the register access request.

Abstract: In an environment in which a processor operates a hypervisor and multiple guest partitions operating under the hypervisor's control, it is desirable to allow a guest partition access to a physical memory device without decreasing system performance. Accordingly, a conversion instruction for converting a logical address to a real address, i.e., an LTOR instruction, executable from a guest partition, is added to the processor. Upon the guest partition's execution of the conversion instruction with the logical address specified, the processor converts the logical address to an encrypted real address, and returns it to the guest partition. The guest partition is then able to pass the encrypted real address to an accelerator that converts the encrypted real address to a real address in order to access the memory device using the real address.

Abstract: A technique for register mapping in a virtual system includes preparing a register pool that includes a plurality of registers for mapping. A mapping table is prepared that has a register identifier (ID) and information related to each of a plurality of parameters that express an operational state of the virtual system for each of the registers. At the time a register access request is issued by a hardware thread, the register ID for an access target and information related to each of the plurality of parameters that express the operational state during operation is acquired. One of the registers, for which the acquired register ID and information related to each of the plurality of parameters match the register ID and information for each of the plurality of parameters within the mapping table, is set as a mapped register to be accessed per the register access request.

Abstract: In an environment in which a processor operates a hypervisor and multiple guest partitions operating under the hypervisor's control, it is desirable to allow a guest partition access to a physical memory device without decreasing system performance. Accordingly, a conversion instruction for converting a logical address to a real address, i.e., an LTOR instruction, executable from a guest partition, is added to the processor. Upon the guest partition's execution of the conversion instruction with the logical address specified, the processor converts the logical address to an encrypted real address, and returns it to the guest partition. The guest partition is then able to pass the encrypted real address to an accelerator that converts the encrypted real address to a real address in order to access the memory device using the real address.

Abstract: In an information processing apparatus, an operation receiving section receives an operation performed on a display. In response to the operation to call up a setting screen, a menu information generating section generates menu information in which a setting button requesting a setting conflicting with the current state is displayed in a highlighted mode. In response to the operation of pressing the highlighted setting button, an influence information generating section generates influence information on the current state conflicting with the setting to be made by pressing the setting button. In addition, a display control section controls the display of a setting screen, including the menu information, and also controls the display of a setting screen, including the influence information when the influence information is generated.