Abstract: A memory module comprising a plurality of identical wiring boards stacked in a multi-stage fashion provides with only one decoder mounted on one of the plurality of identical wiring boards and a plurality of inter-pattern connection means arranged on the wiring boards each for selectively connecting a first wiring pattern connected to said output of said decoder and a second wiring pattern connected to said at least one IC memory chip on each wiring board.

Abstract: A semiconductor data storage apparatus having a plurality of memory devices which are switched to a predetermined mode when a software command has been written, which have waiting time during execution of the command after the command has been written and from which data can be collectively erased, the semiconductor data storage apparatus being arranged to shorten the time required to erase data. A memory device is activated in response to a memory selection signal supplied by a decoder, a write enable signal, which has been, by an AND gate circuit, selectively supplied in response to the selection signal, brings the memory device into a write mode, upper address signals are sequentially switched during waiting time during execution of erasure after an erase command has been written so as to sequentially write erase commands on next memory devices by the decoder and AND gate circuits.

Abstract: A semiconductor data storage apparatus having a plurality of memory devices which are switched to a predetermined mode when a software command has been written, which have waiting time during execution of the command after the command has been written and from which data can be collectively erased, the semiconductor data storage apparatus being arranged to shorten the time required to erase data. A memory device is activated in response to a memory selection signal supplied by a decoder, a write enable signal, which has been, by an AND gate circuit, selectively supplied in response to the selection signal, brings the memory device into a write mode, upper address signals are sequentially switched during a waiting time during execution of erasure after an erase command has been written so as to sequentially write erase commands on next memory devices by the decoder and AND gate circuits.