Patents by Inventor Masanori Numano

Masanori Numano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8232197
    Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: July 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
  • Publication number: 20100003816
    Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.
    Type: Application
    Filed: September 9, 2009
    Publication date: January 7, 2010
    Inventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
  • Patent number: 7605076
    Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: October 20, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
  • Publication number: 20060189145
    Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 24, 2006
    Inventors: Makoto Honda, Kaori Yomogihara, Kazuhiro Murakami, Masanori Numano, Takahito Nagamatsu, Hideaki Harakawa, Hideto Matsuyama, Hirokazu Ezawa, Hisashi Kaneko
  • Patent number: 6222252
    Abstract: A semiconductor substrate is provided which can efficiently exhibit intrinsic gettering (IG) effect, is less likely to cause slipping or dislocation, and causes no significant lowering in mechanical strength. The semiconductor substrate has bulk micro defects dispersed at a density of not less than 1011 micro defects/cm3 in the interior thereof.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: April 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Numano, Moriya Miyashita
  • Patent number: 5951755
    Abstract: A manufacturing method for manufacturing a semiconductor substrate has first annealing step for annealing silicon single crystal to permit oxygen embryos or oxygen precipitations grown from the oxygen embryos precipitating in a predetermined region and a second annealing step for permitting said oxygen embryos or said oxygen precipitations to contract using a second temperature range higher than the first temperature range, said second temperature range being high enough to contract said oxygen embryos and low enough to prevent redistribution of boron from affecting to device characteristics, to form a denuded zone in said predetermined region at the principal surface. An inspection method for inspecting a semiconductor substrate further has measuring step, subsequent to said first and second annealing steps for measuring the density of oxygen embryos grown into oxygen precipitations among those precipitated in said silicon single crystal.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: September 14, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Moriya Miyashita, Masanobu Ogino, Tadahide Hoshi, Masanori Numano, Shuichi Samata, Akiko Sekihara, Keiko Akita
  • Patent number: 5739575
    Abstract: Element isolation technique for LSIs having a fine pattern of sub-micron class or finer. A high strained region doped with impurities at a high concentration is formed under, and remote from, a buried insulating material (dielectrics) layer for element isolation. With this buried dielectrics element isolation (BDEI) structure, since the high strained layer exists just under the buried dielectrics layer, crystal defects generated near the buried dielectrics layer due to strain caused by a difference of thermal expansion coefficient between a semiconductor layer and the buried dielectrics layer, are moved toward the high strained layer. Accordingly, the crystal defects do not reach an active region where active elements are formed, so that leakage current in the p-n junction formed in the active layer can be advantageously reduced.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: April 14, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Numano, Norihiko Tsuchiya, Hiroyasu Kubota, Yoshiaki Matsushita, Yoshiki Hayashi, Yukihiro Ushiku, Atsushi Yagishita, Satoshi Inaba, Yasunori Okayama, Minoru Takahashi
  • Patent number: 5738942
    Abstract: Provided is a process for producing a semiconductor silicon wafer by which an intrinsic gettering effect can be improved and at the same time the top side can be made free from faults. A silicon ingot is produced and sliced to obtain silicon wafers. Then, a polycrystal silicon depositing film is formed on one side of a silicon wafer, which is subjected to a heat treatment in an inert gas, a reducing gas or a mixture thereof to discharge oxygen from the vicinity of the other side. Alternatively, after discharging oxygen from the silicon wafer by a heat treatment, a polycrystal silicon depositing film may be formed on one side of the silicon wafer.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: April 14, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kubota, Masakatu Kojima, Norihiko Tsuchiya, Shuichi Samata, Masanori Numano, Yoshihiro Ueno
  • Patent number: 5675176
    Abstract: A semiconductor device has a semiconductor substrate having a groove, and a semiconductor element formed in a surface region of the semiconductor substrate. A substance having a thermal expansion coefficient different from the semiconductor substrate is embedded in at least a portion of the groove, a crystal defect is generated from the region near the bottom of the groove in the semiconductor substrate, thereby alleviating stress and strain in other regions of the semiconductor substrate, such that such regions cannot generate crystal defects in a region necessary for a circuit operation of the semiconductor element of the surface region.
    Type: Grant
    Filed: September 15, 1995
    Date of Patent: October 7, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihiro Ushiku, Atsushi Yagishita, Satoshi Inaba, Minoru Takahashi, Masanori Numano, Yoshiki Hayashi, Yoshiaki Matsushita, Yasunori Okayama, Hiroyasu Kubota, Norihiko Tsuchiya
  • Patent number: 5534294
    Abstract: Provided is a process for producing a semiconductor silicon wafer by which an intrinsic gettering effect can be improved and at the same time the top side can be made free from faults. A silicon ingot is produced and sliced to obtain silicon wafers. Then, a polycrystal silicon depositing film is formed on one side of a silicon wafer, which is subjected to a heat treatment in an inert gas, a reducing gas or a mixture thereof to discharge oxygen from the vicinity of the other side. Alternatively, after discharging oxygen from the silicon wafer by a heat treatment, a polycrystal silicon depositing film may be formed on one side of the silicon wafer.
    Type: Grant
    Filed: July 22, 1994
    Date of Patent: July 9, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kubota, Masakatu Kojima, Norihiko Tsuchiya, Shuichi Samata, Masanori Numano, Yoshihiro Ueno
  • Patent number: 5508800
    Abstract: There are provided a method of inspecting and evaluating semiconductor substrates, good quality semiconductor substrates, a method of manufacturing good quality semiconductor substrates, and a method of manufacturing semiconductor devices using good quality semiconductor substrates.A semiconductor substrate is processed with aqueous basic solution. In this process, the substrate is dipped in the aqueous solution or exposed to a vapor of the aqueous solution. With this process, the surface of the substrate is selectively etched. The substrate surface after the etching process is radiated with a laser beam to measure a light scattered point density. The quality of the substrate can be judged in accordance with the measured density. A thermal treatment may be carried out before or after processing the substrate with the aqueous basic solution. The thermal treatment considerably changes the fine defect density on the surface of the substrate.
    Type: Grant
    Filed: March 16, 1993
    Date of Patent: April 16, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Moriya Miyashita, Hachiro Hiratsuka, Atsuko Kubota, Shuichi Samata, Masanori Numano, Hiroyuki Fukui