Abstract: A liquid crystal display device includes pixels, each of which includes a first transistor and a second transistor. The size of the first transistor is larger than the size of the second transistor. In addition, channel widths and gate widths for the first transistor are larger than those of the second transistor. Also, the first transistor is located to be closer to a drain signal line provided for the pixel than the second transistor. In normal operation, the first transistor is coupled to the drain signal line and the second transistor is floating. However, if an abnormality occurs in the first transistor, it is cut off from the drain signal line and the second transistor is connected to the drain signal line by a repair line.

Abstract: A liquid crystal display device includes pixels, each of which includes a first transistor and a second transistor. The size of the first transistor is larger than the size of the second transistor. In addition, channel widths and gate widths for the first transistor are larger than those of the second transistor. Also, the first transistor is located to be closer to a drain signal line provided for the pixel than the second transistor. In normal operation, the first transistor is coupled to the drain signal line and the second transistor is floating. However, if an abnormality occurs in the first transistor, it is cut off from the drain signal line and the second transistor is connected to the drain signal line by a repair line.

Abstract: A normal transistor CTFT connected to a data signal line DL and a pixel electrode PX and a spare transistor FTFT in a floating state are formed on a gate line GL. When an operational abnormality occurs in the normal transistor CTFT, the normal transistor CTFT is cut off from the data signal line DL and is cut off from the pixel electrode PX connected via a through hole TH by cutting lines CL. Thereafter, the spare transistor FTFT is connected to the data signal line DL and the pixel electrode PX by repair lines RL.

Abstract: A normal transistor CTFT connected to a data signal line DL and a pixel electrode PX and a spare transistor FTFT in a floating state are formed on a gate line GL. When an operational abnormality occurs in the normal transistor CTFT, the normal transistor CTFT is cut off from the data signal line DL and is cut off from the pixel electrode PX connected via a through hole TH by cutting lines CL. Thereafter, the spare transistor FTFT is connected to the data signal line DL and the pixel electrode PX by repair lines RL.