Patents by Inventor Masanori Oozeki

Masanori Oozeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Delay circuit for gate-array LSI
    Patent number: 4700089
    Abstract: A delay circuit for a gate-array LSI including at least one inverter having a plurality of P-channel transistors (Q.sub.1p to Q.sub.4p) and a plurality of N-channel transistors (Q.sub.1n to Q.sub.4n) connected in series. The P-channel/N-channel transistors are driven by an input potential (IN), and the common output of the innermost pair of P-channel/N-channel transistors generates an output.
    Type: Grant
    Filed: August 20, 1985
    Date of Patent: October 13, 1987
    Assignee: Fujitsu Limited
    Inventors: Shigeru Fujii, Masanori Oozeki