Patents by Inventor Masanori Sakata

Masanori Sakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973432
    Abstract: First switches include first electrodes, which are mutually connected with each other via a first internal bus bar, and second electrodes, which are mutually connected with each other via a second internal bus bar. A first resin member encapsulates the first switches and the first and second internal bus bars. Second switches include third electrodes, which are mutually connected with each other via a third internal bus bar, and fourth electrodes, which are mutually connected with each other via a fourth internal bus bar. A second resin member that encapsulates the second switches and the third and fourth internal bus bars. The second module is arranged alongside with the first module. The second internal bus bar and the third internal bus bar are partially exposed from the first resin member and the second resin member, respectively, and are directly joined with each other.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: April 30, 2024
    Assignee: DENSO CORPORATION
    Inventors: Hiromi Ichijyo, Yuu Yamahira, Kazuya Takeuchi, Masanori Sakata, Masayoshi Nishihata
  • Patent number: 11973433
    Abstract: A first module includes a first switch having a first electrode and a second electrode; a second switch having a third electrode and a fourth electrode; a second internal bus bar connecting the second electrode with the third electrode; and a first resin member encapsulating those components. A second module with includes a third switch having a fifth electrode and a sixth electrode; a fourth switch having a seventh electrode and an eighth electrode; a fifth internal bus bar connecting the sixth electrode with the seventh electrode; and a second resin member encapsulating those components. At least one of a first terminal of the second internal bus bar exposed from the first resin member and a second terminal of the fifth internal bus bar exposed from the second resin member extends toward the other and are directly joined with each other.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: April 30, 2024
    Assignee: DENSO CORPORATION
    Inventors: Hiromi Ichijyo, Yuu Yamahira, Kazuya Takeuchi, Masanori Sakata, Masayoshi Nishihata
  • Publication number: 20220200471
    Abstract: A first module includes a first switch having a first electrode and a second electrode; a second switch having a third electrode and a fourth electrode; a second internal bus bar connecting the second electrode with the third electrode; and a first resin member encapsulating those components. A second module with includes a third switch having a fifth electrode and a sixth electrode; a fourth switch having a seventh electrode and an eighth electrode; a fifth internal bus bar connecting the sixth electrode with the seventh electrode; and a second resin member encapsulating those components. At least one of a first terminal of the second internal bus bar exposed from the first resin member and a second terminal of the fifth internal bus bar exposed from the second resin member extends toward the other and are directly joined with each other.
    Type: Application
    Filed: March 9, 2022
    Publication date: June 23, 2022
    Applicant: DENSO CORPORATION
    Inventors: Hiromi ICHIJYO, Yuu YAMAHIRA, Kazuya TAKEUCHI, Masanori SAKATA, Masayoshi NISHIHATA
  • Publication number: 20220200470
    Abstract: First switches include first electrodes, which are mutually connected with each other via a first internal bus bar, and second electrodes, which are mutually connected with each other via a second internal bus bar. A first resin member encapsulates the first switches and the first and second internal bus bars. Second switches include third electrodes, which are mutually connected with each other via a third internal bus bar, and fourth electrodes, which are mutually connected with each other via a fourth internal bus bar. A second resin member that encapsulates the second switches and the third and fourth internal bus bars. The second module is arranged alongside with the first module. The second internal bus bar and the third internal bus bar are partially exposed from the first resin member and the second resin member, respectively, and are directly joined with each other.
    Type: Application
    Filed: March 9, 2022
    Publication date: June 23, 2022
    Applicant: DENSO CORPORATION
    Inventors: Hiromi ICHIJYO, Yuu YAMAHIRA, Kazuya TAKEUCHI, Masanori SAKATA, Masayoshi NISHIHATA
  • Publication number: 20100000470
    Abstract: A wafer-positioning mechanism includes a susceptor having an upper surface for supporting a wafer thereon, which is slanted with respect to a horizontal plane at an angle such that the wafer on the upper surface slides with an aid and does not slide without the aid. The aid is a gas flowing out of the upper surface against the reverse side of the wafer facing the upper surface. The upper surface has a protrusion for stopping the wafer from sliding beyond the protrusion in the sliding direction by contacting an edge of the wafer where the wafer is positioned on the upper surface for wafer processing.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 7, 2010
    Applicant: ASM JAPAN K.K.
    Inventor: Masanori Sakata
  • Publication number: 20050215096
    Abstract: The present invention was made considering these problems, and has the objective of providing an audio-video jack provided with a defense wall which prevents a foreign object such as a wire from being inserted through the tip of the audio-video jack from the outside and penetrating to the back of the audio-video jack. An audio-video jack 1 has a terminal unit 2. A housing 6 installed as a single unit with the terminal unit 2 is installed on one end of the terminal unit 2. A defense wall 10 is installed on the rear section of the housing 6, and when a foreign object such as a wire is inserted from the terminal unit 2 of the audio-video jack 1, it blocks a foreign object from penetrating to the back of the audio-video jack 1.
    Type: Application
    Filed: March 22, 2005
    Publication date: September 29, 2005
    Applicant: ORION ELECTRIC CO., LTD.
    Inventor: Masanori Sakata
  • Patent number: 5225376
    Abstract: According to the principles of this invention, a polysilicon layer in a semiconductor device is shaped so that in subsequent processing steps a uniform topology is achieved. In particular, a first layer, typically polysilicon, is overlain by a second layer, typically spin-on glass, which is in turn overlain by a mask layer. An opening is formed in the mask layer and the second layer. An isotropic etchant is applied to the structure after the opening is formed. The etchant is formulated to have a differential etch rate in the first and the second layers so that the first layer after etching has an edge surface with a taper of less than 60.degree. and preferably about 45.degree..
    Type: Grant
    Filed: January 13, 1992
    Date of Patent: July 6, 1993
    Assignee: NEC Electronics, Inc.
    Inventors: Lloyd W. Feaver, Masanori Sakata
  • Patent number: 5093700
    Abstract: A FET transistor has a gate structure consisting of at least three layers of polysilicon with a thin oxide layer on the order of atoms thick separating each of the layers. A method for formation of the multilayer gate structure and the formation of resistors comprised of layers of polysilicon separated by oxide layers are also provided.
    Type: Grant
    Filed: April 8, 1991
    Date of Patent: March 3, 1992
    Assignee: NEC Electronics Inc.
    Inventor: Masanori Sakata
  • Patent number: 4558338
    Abstract: The present invention relates to cross-sectional shape of a silicon gate electrode of an insulated gate field effect transistor. The gate electrode is composed of polycrystalline silicon, and its length, in cross section, gradually increases from the surface contacting to the gate insulating film toward the central portion thereof and then gradually decreases toward the upper surface thereof. The central portion of the polycrystalline silicon has the largest length in the source-drain direction and contains small amount of SiO.sub.2 particles. Relying upon this gate shape, the portion having largest length, can be used as a mask to introduce impurities in a self-aligned manner to form source and drain regions. The thus formed source and drain regions create small capacity relative to the gate electrode. Therefore, a high speed transistor is realized.
    Type: Grant
    Filed: August 15, 1983
    Date of Patent: December 10, 1985
    Assignee: Nec Corporation
    Inventor: Masanori Sakata