Patents by Inventor Masanori Shindo

Masanori Shindo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11742305
    Abstract: A semiconductor device includes a lower insulating layer formed on a primary surface of a semiconductor substrate; a sealing layer formed in contact with a top surface of the lower insulating layer; and a conductive member including a first conductive member formed on the sealing layer and having a first film thickness and a second conductive member formed on the sealing layer in contact with a first conductive member and having a second film thickness that is smaller than the first film thickness.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: August 29, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Publication number: 20230253326
    Abstract: A foundation portion and a conductive base portion disposed on the foundation portion are formed on a temporary support, a semiconductor element electrically connected to the base portion is disposed on a side of the temporary support on which the foundation portion and the base portion are formed, and an insulating layer coming into a state of burying the foundation portion, the base portion, and the semiconductor element is formed on the temporary support. Subsequently, surfaces of the foundation portion and the insulating layer on a side of the temporary support are exposed by removing the temporary support, and the exposed foundation portion is further removed, thereby disposing the base portion in a state of being more recessed than the surface of the insulating layer. An external connection terminal is formed on the exposed base portion to manufacture the semiconductor package.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Masanori Shindo
  • Patent number: 11664314
    Abstract: A foundation portion and a conductive base portion disposed on the foundation portion are formed on a temporary support, a semiconductor element electrically connected to the base portion is disposed on a side of the temporary support on which the foundation portion and the base portion are formed, and an insulating layer coming into a state of burying the foundation portion, the base portion, and the semiconductor element is formed on the temporary support. Subsequently, surfaces of the foundation portion and the insulating layer on a side of the temporary support are exposed by removing the temporary support, and the exposed foundation portion is further removed, thereby disposing the base portion in a state of being more recessed than the surface of the insulating layer. An external connection terminal is formed on the exposed base portion to manufacture the semiconductor package.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 30, 2023
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Masanori Shindo
  • Publication number: 20230094425
    Abstract: There is provided a semiconductor device including: a circuit region formed on a semiconductor substrate; a first insulating film covering at least a portion of a region on the semiconductor substrate that includes an upper portion of the circuit region; redistribution wiring disposed on the first insulating film; a coil formed by the redistribution wiring on the first insulating film, the coil being connected to the circuit region; a first soft magnetic material film disposed in an aperture portion of the first insulating film, the aperture portion being provided at a lower portion of the coil; and a second soft magnetic material film that is disposed on the first soft magnetic material film, the second soft magnetic material film covering at least a portion of the coil.
    Type: Application
    Filed: September 29, 2022
    Publication date: March 30, 2023
    Inventor: MASANORI SHINDO
  • Patent number: 11600589
    Abstract: A semiconductor device including a terminal that is formed using copper, that is electrically connected to a circuit element, and that includes a formation face formed with a silver-tin solder bump such that a nickel layer is interposed between the terminal and the solder bump, wherein the nickel layer is formed on a region corresponding to part of the formation face.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: March 7, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Patent number: 11545452
    Abstract: A semiconductor device including a semiconductor substrate including an electrode; a wire connected to the electrode; a first insulating film including a first opening that partially exposes the wire; a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; and a solder film on a surface of the base portion. Solder included in the solder film is fused by a first heat treatment, and the recess is filled with the fused solder.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: January 3, 2023
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Patent number: 11538775
    Abstract: A semiconductor device includes wiring that is formed by a conductive body extending, via an insulating film, on a front surface of a semiconductor substrate, and an insulating layer that covers the front surface of the semiconductor substrate including the wiring. Gaps are provided extending from an upper surface of the wiring to a lower portion of the insulating film.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: December 27, 2022
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Publication number: 20210242155
    Abstract: Provided is a semiconductor device including a terminal that is formed using copper, that is electrically connected to a circuit element, and that includes a formation face formed with a silver-tin solder bump such that a nickel layer is interposed between the terminal and the solder bump, wherein the nickel layer is formed on a region corresponding to part of the formation face.
    Type: Application
    Filed: February 1, 2021
    Publication date: August 5, 2021
    Inventor: MASANORI SHINDO
  • Publication number: 20210242145
    Abstract: A semiconductor device includes wiring that is formed by a conductive body extending, via an insulating film, on a front surface of a semiconductor substrate, and an insulating layer that covers the front surface of the semiconductor substrate including the wiring. Gaps are provided extending from an upper surface of the wiring to a lower portion of the insulating film.
    Type: Application
    Filed: February 1, 2021
    Publication date: August 5, 2021
    Inventor: MASANORI SHINDO
  • Publication number: 20210233878
    Abstract: A semiconductor device includes a lower insulating layer formed on a primary surface of a semiconductor substrate; a sealing layer formed in contact with a top surface of the lower insulating layer; and a conductive member including a first conductive member formed on the sealing layer and having a first film thickness and a second conductive member formed on the sealing layer in contact with a first conductive member and having a second film thickness that is smaller than the first film thickness.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Masanori SHINDO
  • Patent number: 11004813
    Abstract: A semiconductor device includes a lower insulating layer formed on a primary surface of a semiconductor substrate; a sealing layer formed in contact with a top surface of the lower insulating layer; and a conductive member including a first conductive member formed on the sealing layer and having a first film thickness and a second conductive member formed on the sealing layer in contact with a first conductive member and having a second film thickness that is smaller than the first film thickness.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 11, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Publication number: 20210118831
    Abstract: A semiconductor device manufacturing method including preparing a semiconductor substrate including an electrode; forming a wire connected to the electrode; forming a first insulating film including a first opening that partially exposes the wire; forming a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; forming a solder film on a surface of the base portion; and fusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Inventor: Masanori Shindo
  • Patent number: 10910331
    Abstract: A semiconductor device manufacturing method including preparing a semiconductor substrate including an electrode; forming a wire connected to the electrode; forming a first insulating film including a first opening that partially exposes the wire; forming a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; forming a solder film on a surface of the base portion; and fusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: February 2, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Publication number: 20200312777
    Abstract: A foundation portion and a conductive base portion disposed on the foundation portion are formed on a temporary support, a semiconductor element electrically connected to the base portion is disposed on a side of the temporary support on which the foundation portion and the base portion are formed, and an insulating layer coming into a state of burying the foundation portion, the base portion, and the semiconductor element is formed on the temporary support. Subsequently, surfaces of the foundation portion and the insulating layer on a side of the temporary support are exposed by removing the temporary support, and the exposed foundation portion is further removed, thereby disposing the base portion in a state of being more recessed than the surface of the insulating layer. An external connection terminal is formed on the exposed base portion to manufacture the semiconductor package.
    Type: Application
    Filed: March 12, 2020
    Publication date: October 1, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Masanori Shindo
  • Publication number: 20190164918
    Abstract: A semiconductor device includes a lower insulating layer formed on a primary surface of a semiconductor substrate; a sealing layer formed in contact with a top surface of the lower insulating layer; and a conductive member including a first conductive member formed on the sealing layer and having a first film thickness and a second conductive member formed on the sealing layer in contact with a first conductive member and having a second film thickness that is smaller than the first film thickness.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 30, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Masanori SHINDO
  • Publication number: 20190139918
    Abstract: A semiconductor device manufacturing method includes: preparing a semiconductor substrate including an electrode; forming a wire connected to the electrode; forming a first insulating film including a first opening that partially exposes the wire; forming a base portion that is connected to a portion of the wire exposed via the first opening, and that comprises a conductor including a recess corresponding to the first opening; forming a solder film on a surface of the base portion; and fusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 9, 2019
    Inventor: Masanori Shindo
  • Patent number: 10141279
    Abstract: A semiconductor device includes a semiconductor substrate, a conductor provided on a main surface of the semiconductor substrate, an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor, and an external connection terminal connected to the portion of the conductor exposed from the opening. In a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 27, 2018
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Masanori Shindo
  • Publication number: 20180182725
    Abstract: A semiconductor device includes a semiconductor substrate, a conductor provided on a main surface of the semiconductor substrate, an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor, and an external connection terminal connected to the portion of the conductor exposed from the opening. In a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 28, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Masanori SHINDO
  • Publication number: 20120301552
    Abstract: A compound represented by the following formula (1), a pharmaceutically acceptable salt thereof or an optically active form thereof: wherein each symbol is as defined in the specification. A compound having a calcium-sensing receptor antagonistic action, a pharmaceutical composition comprising the compound, particularly a calcium receptor antagonist and a therapeutic drug for osteoporosis are provided.
    Type: Application
    Filed: December 23, 2011
    Publication date: November 29, 2012
    Applicant: JAPAN TOBACCO INC.
    Inventors: Yuko Shinagawa, Teruhiko Inoue, Toshihiro Kiguchi, Taku Ikenogami, Naoki Ogawa, Kenji Fukuda, Takashi Nakagawa, Masanori Shindo, Yuki Soejima
  • Publication number: 20090326058
    Abstract: A compound represented by the following formula (1), a pharmaceutically acceptable salt thereof or an optically active form thereof: wherein each symbol is as defined in the specification. A compound having a calcium-sensing receptor antagonistic action, a pharmaceutical composition comprising the compound, particularly a calcium receptor antagonist and a therapeutic drug for osteoporosis are provided.
    Type: Application
    Filed: March 27, 2009
    Publication date: December 31, 2009
    Applicant: JAPAN TOBACCO INC.
    Inventors: YUKO SHINAGAWA, TERUHIKO INOUE, TOSHIHIRO KIGUCHI, TAKU IKENOGAMI, NAOKI OGAWA, KENJI FUKUDA, TAKASHI NAKAGAWA, MASANORI SHINDO, YUKI SOEJIMA