Patents by Inventor Masanori Tanaka

Masanori Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240247347
    Abstract: In the production of a grain-oriented electrical steel sheet by heating a steel slab containing, in mass %, C: 0.02 to 0.10%, Si: 2.5 to 5.5%, Mn: 0.01 to 0.30%, S: 0.0010 to 0.040%, Se: 0 to 0.040%, sol. Al: 0.010 to 0.040%; and N: 0.004 to 0.020% to 1300° C. or higher; subsequently performing hot rolling, hot-band annealing as necessary, cold rolling, and primary recrystallization annealing which also serves as decarburization annealing; applying an annealing separator on the surface of the steel sheet; and performing finishing annealing, edge cracks that may occur in the hot rolling are effectively prevented by keeping a slab lateral face temperature at a time of starting rough rolling during the hot rolling equal to or lower than a temperature Te defined by the following Expression Te=?120000 [% S]2+1400 (1) and carrying out width reduction after at least one pass in the rough rolling.
    Type: Application
    Filed: May 26, 2022
    Publication date: July 25, 2024
    Applicant: JFE Steel Corporation
    Inventors: Masanori Takenaka, Takeshi Imamura, Takaaki Tanaka, Hiroi Yamaguchi
  • Publication number: 20240238785
    Abstract: The present disclosure is to provide a microanalysis chip in which: a first channel chamber has a reference electrode arranged therein, the reference electrode having a surface on which an ion crystal having specimen solubility is arranged; a second channel chamber has a working electrode arranged therein; and a first channel and a second channel are configured so that, when a time period required for a specimen to reach the ion crystal after the specimen is dispensed to a dispensing section is represented by T1 and a time period required for the specimen to reach the working electrode after the specimen is dispensed to the dispensing section is represented by T2, the time period T1 and the time period T2 satisfy a relationship of T1>T2.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: KATSUICHI ABE, FUKA ENOKIDO, JUN MIURA, HARUNOBU MAEDA, MASANORI TANAKA, MAKOTO FUKATSU, AKIHISA MATSUKAWA, YASUKAZU IKAMI, Keiji Miyazaki, TAKESHI YAMAMOTO
  • Publication number: 20240238780
    Abstract: An object is to provide a micro-analysis chip with which stable ion concentration measurement can be performed without increasing a chip size or prolonging a measurement time. In order to achieve this object, the following micro-analysis chip is provided. That is, provided is a micro-analysis chip when an average areal velocity which is an area of a region that a specimen has permeated during a period until a dispensed specimen reaches a reference electrode is represented by V1, and when an average areal velocity which is an area of a region that the specimen has permeated during a period until the dispensed specimen fills an inside of a first channel chamber after the dispensed specimen has reached the reference electrode is represented by V2, the average areal velocity V1 and the average areal velocity V2 satisfy a relationship of V1>V2.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: FUKA ENOKIDO, MAKOTO FUKATSU, JUN MIURA, MASANORI TANAKA, HARUNOBU MAEDA, KATSUICHI ABE, AKIHISA MATSUKAWA, YASUKAZU IKAMI, Keiji Miyazaki, TAKESHI YAMAMOTO
  • Patent number: 12040486
    Abstract: According to one embodiment, an electrode is provided. The electrode includes a current collector and an active material-containing layer formed on the current collector. The active material-containing layer contains a lithium nickel cobalt manganese composite oxide and a lithium cobalt composite oxide. Pore size distribution obtained by mercury intrusion porosimetry for the active material-containing layer has a first peak top indicating a highest intensity I1 within a pore size range of from 0.1 ?m to 1 ?m and a second peak top indicating an intensity I2 which is a second highest intensity after the highest intensity I1 within the pore size range of from 0.1 ?m to 1 ?m. A pore size at the first peak top is smaller than a pore size at the second peak top.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: July 16, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keigo Hoshina, Dai Yamamoto, Tetsuro Kano, Masanori Tanaka, Yuki Watanabe, Nobuyasu Negishi
  • Patent number: 12027672
    Abstract: According to one embodiment, a battery includes an external container, an electrode group, and a sealing plate. The electrode group includes a positive electrode and a negative electrode wound in a flat shape with an insulating layer interposed therebetween. Thicknesses TE of the positive and negative electrodes are each from 0.03 mm to 0.08 mm. A first direction is orthogonal to a winding axis direction of the electrode group. A second direction is parallel to the winding axis direction. The thicknesses TE of each electrode, a thickness TW of the electrode group in the third direction orthogonal to the first and second directions, and an innermost circumferential height HIC of the electrode group in the first direction satisfy 0.02?(TE×TW)/HIC?0.04.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: July 2, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masanori Tanaka, Tatsuya Shinoda, Yasuaki Murashi, Makoto Kobayashi, Koichi Takeshita, Masahiro Murata
  • Patent number: 11970390
    Abstract: The present disclosure provides a method for producing a microchannel device, which can form a channel that has high hydrophobicity, high solvent resistance as well, and also resistance to heat and damage, on demand with high accuracy, and produces the microchannel device at a low cost, while having high productivity. The method for producing a microchannel device includes: forming a channel pattern from a hydrophobic resin on a porous substrate by an electrophotographic method; melting the channel pattern by heat to allow the channel pattern to permeate into the porous substrate, thereby forming a channel in the inside of the porous substrate.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: April 30, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Yamamoto, Jun Miura, Keiji Miyazaki, Hiroki Tanaka, Makoto Fukatsu, Akihisa Matsukawa, Takayuki Kanazawa, Keigo Mizusawa, Masanori Seki, Masanori Tanaka
  • Patent number: 11967720
    Abstract: An electrode according to an embodiment contains an electrode mixture layer containing an active material and a conductive assistant. In a logarithmic differential pore volume distribution by a mercury intrusion method, the electrode mixture layer satisfies: a ratio P1/P2 within a range of 2 or more and less than 8, and a ratio S1/S2 within a range of 3 or more and less than 10. P1 is a value of a maximum logarithmic differential pore volume in a pore diameter range of 0.1 ?m or more and 1 ?m or less. P2 is a value of a logarithmic differential pore volume of a pore diameter of 0.03 ?m. S1 is an integrated value in a pore diameter range of 0.1 ?m or more and 1 ?m or less. S2 is an integrated value in a pore diameter range of more than 0 ?m and less than 0.1 ?m.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 23, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuki Watanabe, Dai Yamamoto, Toshitada Nakazawa, Tetsuro Kano, Masanori Tanaka
  • Publication number: 20240124774
    Abstract: A Cd-free blue fluorescent quantum dot with a narrow fluorescence FWHM. The quantum dot does not contain cadmium and its fluorescence FWHM is 25 nm or less. The quantum dot is preferably a nanocrystal containing zinc and selenium or zinc and selenium and sulfur. Further, the quantum dot preferably has a core-shell structure in which the nanocrystal serves as a core and the surface of the core is coated with a shell.
    Type: Application
    Filed: November 3, 2023
    Publication date: April 18, 2024
    Applicant: NS MATERIALS INC.
    Inventors: Yuko OGURA, Yuka TAKAMIZUMA, Kazunori IIDA, Emi TSUTSUMI, Masanori TANAKA, Soichiro NIKATA
  • Publication number: 20240064401
    Abstract: There is provided a light receiving element capable of obtaining a signal with high autofocus performance while suppressing image quality degradation, an imaging device, and a correction processing method. The light receiving element includes: a first pixel that includes a plurality of photoelectric conversion units configured to share a first on-chip lens, receive incident light from a pupil region of an optical system via the first on-chip lens, and perform photoelectric conversion; and a second pixel that includes a plurality of photoelectric conversion units configured to share a second on-chip lens, receive the incident light from the pupil region of the optical system via the second on-chip lens, and perform the photoelectric conversion. The second pixel has lower transmittance on an outer side of the pupil region in which the first pixel is capable of receiving light as compared with the transmittance of the pupil region.
    Type: Application
    Filed: November 18, 2021
    Publication date: February 22, 2024
    Inventor: MASANORI TANAKA
  • Patent number: 11845890
    Abstract: Provided is a Cd-free blue fluorescent quantum dot with a narrow fluorescence FWHM. The quantum dot does not contain cadmium and its fluorescence FWHM is 25 nm or less. The quantum dot is preferably a nanocrystal containing zinc and selenium or zinc and selenium and sulfur. Further, the quantum dot preferably has a core-shell structure in which the nanocrystal serves as a core and the surface of the core is coated with a shell.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: December 19, 2023
    Assignee: NS MATERIALS INC.
    Inventors: Yuko Ogura, Yuka Takamizuma, Kazunori Iida, Emi Tsutsumi, Masanori Tanaka, Soichiro Nikata
  • Publication number: 20230390765
    Abstract: It is possible to provide a microchannel device with excellent resistance to bending and suppressed deterioration in inspection accuracy. A microchannel device has a channel sandwiched between channel walls formed in an inside a porous substrate, the channel wall contains a thermoplastic resin and a wax, and a proportion of the wax in an area of a surface side of the channel wall facing the channel is higher than a proportion of the wax inside the channel wall.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Inventors: AKIHISA MATSUKAWA, MAKOTO FUKATSU, MASANORI TANAKA, TAKESHI YAMAMOTO, Keiji Miyazaki, JUN MIURA, HARUNOBU MAEDA, FUKA ENOKIDO, YUHEI TERUI
  • Publication number: 20230390764
    Abstract: The present disclosure provides a microchannel device that has a channel sandwiched between channel walls formed in an inside of a porous substrate, wherein the channel wall contains a thermoplastic resin and a colorant, and wherein an abundance ratio of the colorant is higher in the porous substrate surface area of the channel wall than in an internal area of the channel wall. In the configuration of the present disclosure, since more of the colorant exist on the surface side of the porous substrate in the channel wall, the visibility of the channel is increased, and in addition, since the amount of the colorant in the internal portion of the channel wall is small, the elution of the ions contained in the colorant into the specimen is suppressed, and the measurement accuracy is increased.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Inventors: MAKOTO FUKATSU, MASANORI TANAKA, TAKESHI YAMAMOTO, Keiji Miyazaki, JUN MIURA, HARUNOBU MAEDA, FUKA ENOKIDO, AKIHISA MATSUKAWA, YUHEI TERUI
  • Publication number: 20230387166
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a semiconductor substrate which has a first surface and a second surface opposed to each other, and in which a plurality of pixels are arranged in matrix, the semiconductor substrate including a plurality of photoelectric conversion sections that each generate electric charge corresponding to a light receiving amount by photoelectric conversion for each pixel; a first lens disposed for each pixel; a second lens disposed between the semiconductor substrate and the first lens for each photoelectric conversion section; a first separation section provided between adjacent photoelectric conversion sections in each pixel and optically separating the adjacent photoelectric conversion sections from each other; and a second separation section provided between adjacent pixels, optically separating the adjacent pixels from each other, and protruding farther than the first separation section in a light incident direction.
    Type: Application
    Filed: December 3, 2021
    Publication date: November 30, 2023
    Inventor: Masanori Tanaka
  • Patent number: 11831005
    Abstract: According to one embodiment, an electrode group is provided. The electrode group includes a positive electrode active material-containing layer and a negative electrode active material-containing layer. The negative electrode active material-containing layer contains at least one titanium-containing composite oxide selected from the group consisting of a monoclinic niobium titanium composite oxide and an orthorhombic titanium-containing composite oxide. The electrode group satisfies the following formula: 6500?A/B?18500, where A is an area [cm2] of a portion of the negative electrode active material-containing layer that faces the positive electrode active material-containing layer, and B is a thickness [cm] of the electrode group.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: November 28, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keigo Hoshina, Masanori Tanaka, Yasuhiro Harada, Norio Takami
  • Publication number: 20230232647
    Abstract: A quantum dot (QD) dispersion solution includes QD phosphor particles, ligands, and a solvent. Each ligand includes a thiol group and at least one functional group of ester groups and ether groups. The solvent is propylene glycol monomethyl ether acetate.
    Type: Application
    Filed: July 3, 2020
    Publication date: July 20, 2023
    Inventors: Masaki YAMAMOTO, Kazuki GOTO, Yuma YAGUCHI, Soichiro NIKATA, Yuko OGURA, Masanori TANAKA, Yuka TAKAMIZUMA, Tetsuji ITO, Mikihiro TAKASAKI
  • Patent number: 11699717
    Abstract: An image pickup element using an APD is provided. The image pickup element has a first substrate, a second substrate, and a connector. The first substrate is provided with a plurality of light receivers having the APD. The second substrate has a pixel circuit that corresponds to each of the APDs. Additionally, the connector electrically connects the APD and the pixel circuit corresponding to the APD.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: July 11, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masanori Tanaka
  • Publication number: 20230080877
    Abstract: The electroluminescent element includes an anode electrode, a cathode electrode, and a quantum dot (QD) layer including quantum dots and arranged between the anode electrode and the cathode electrode. The quantum dots are Cd-free quantum dots that include at least Zn and Se, and do not include Cd at a mass ratio of 1/30 or greater in relation to Zn. The particle size of each quantum dot is within a range from 3 nm to 20 nm.
    Type: Application
    Filed: February 17, 2020
    Publication date: March 16, 2023
    Inventors: Masaki YAMAMOTO, Hirohisa YAMADA, Yoshihiro UETA, Keisuke KITANO, Kazuki GOTO, Yusuke SAKAKIBARA, Tadashi KOBASHI, Masashi KAGO, Soichiro NIKATA, Yuko OGURA, Masanori TANAKA, Yuka TAKAMIZUMA, Tetsuji ITO
  • Patent number: 11587855
    Abstract: A method of manufacturing a semiconductor device, including: preparing a power semiconductor chip, a lead frame having a die pad part and a terminal part integrally connected to the die pad part, and an insulating sheet in a semi-cured state; disposing the power semiconductor chip on a front surface of the die pad part and performing wiring; encapsulating the lead frame and the power semiconductor chip with an encapsulation raw material in a semi-cured state, to thereby form a semi-cured unit, the terminal part projecting from the semi-cured unit, and a rear surface of the die pad part being exposed from a rear surface of the semi-cured unit; pressure-bonding a front surface of the insulating sheet to the rear surface of the semi-cured unit to cover the rear surface of the die pad part; and curing the semi-cured unit and the insulating sheet by heating.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: February 21, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masanori Tanaka
  • Publication number: 20230050112
    Abstract: A semiconductor device manufacturing method includes a molding step including disposing a control pin between an inlet and a control wire and on a line connecting the inlet and the control wire in a plan view of the semiconductor device, injecting molding resin raw material into a cavity through the inlet, filling the cavity with the molding resin raw material, and sealing a semiconductor chip and a control element disposed on a main current lead frame and a control lead frame. In this way, the flow velocity of the molding resin raw material flowing to the control wire is reduced.
    Type: Application
    Filed: June 24, 2022
    Publication date: February 16, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Masanori TANAKA, Akira FURUTA
  • Publication number: 20230032285
    Abstract: The present invention provides a facility capable of efficiently performing work while maintaining the cleanliness of a location where an article is manufactured, when manufacturing of the article and other work are performed in parallel concurrently; and an implementation method for manufacturing an article by using the facility. The facility comprises a clean room 1, multiple work booths 2 provided inside the clean room 1 and each comprising an entrance and exit, and barrier sections provided along entrances and exits of the multiple work booth 2 and configured to prevent airflow from the outside to the inside through the entrances and exits. The area inside each of the multiple work booths 2 has the same grade of cleanliness as the area that is outside the multiple work booths 2 but is inside the clean room 1.
    Type: Application
    Filed: December 10, 2020
    Publication date: February 2, 2023
    Inventors: Masanori TANAKA, Noriko UMEDA, Naoko TERAO, Atsuko WAKIMURA, Tsuyoshi ISHIKAWA, Nobu MIYAKAWA