Patents by Inventor Masanori Tateyama
Masanori Tateyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Coater/developer, method of coating and developing resist film, and computer readable storing medium
Patent number: 8372480Abstract: A transfer flow is produced in accordance with a process recipe of a process to be carried out. In the transfer flow, a type of modules listed in accordance with a substrate transfer order is associated with a necessary staying time from when the substrate is transferred into a module by a substrate transfer unit to when the substrate is ready to be transferred back to the substrate transfer unit after the corresponding process is finished. A cycle limiting time is determined to be the longest necessary transfer cycle time among those obtained by dividing the necessary staying time by the number of the modules mounted in the coater/developer. The number of the modules to be used is determined to be a value obtained by dividing the necessary staying time by the cycle limiting time or a nearest integer to which the value is raised.Type: GrantFiled: July 7, 2011Date of Patent: February 12, 2013Assignee: Tokyo Electron LimitedInventors: Akira Miyata, Masanori Tateyama -
COATER/DEVELOPER, METHOD OF COATING AND DEVELOPING RESIST FILM, AND COMPUTER READABLE STORING MEDIUM
Publication number: 20110262623Abstract: A transfer flow is produced in accordance with a process recipe of a process to be carried out. In the transfer flow, a type of modules listed in accordance with a substrate transfer order is associated with a necessary staying time from when the substrate is transferred into a module by a substrate transfer unit to when the substrate is ready to be transferred back to the substrate transfer unit after the corresponding process is finished. A cycle limiting time is determined to be the longest necessary transfer cycle time among those obtained by dividing the necessary staying time by the number of the modules mounted in the coater/developer. The number of the modules to be used is determined to be a value obtained by dividing the necessary staying time by the cycle limiting time or a nearest integer to which the value is raised.Type: ApplicationFiled: July 7, 2011Publication date: October 27, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Akira MIYATA, Masanori TATEYAMA -
Coater/developer, method of coating and developing resist film, and computer readable storing medium
Patent number: 8015940Abstract: A transfer flow is produced in accordance with a process recipe of a process to be carried out. In the transfer flow, a type of modules listed in accordance with a substrate transfer order is associated with a necessary staying time from when the substrate is transferred into a module by a substrate transfer unit to when the substrate is ready to be transferred back to the substrate transfer unit after the corresponding process is finished. A cycle limiting time is determined to be the longest necessary transfer cycle time among those obtained by dividing the necessary staying time by the number of the modules mounted in the coater/developer. The number of the modules to be used is determined to be a value obtained by dividing the necessary staying time by the cycle limiting time or a nearest integer to which the value is raised.Type: GrantFiled: October 9, 2008Date of Patent: September 13, 2011Assignee: Tokyo Electron LimitedInventors: Akira Miyata, Masanori Tateyama -
COATER/DEVELOPER, METHOD OF COATING AND DEVELOPING RESIST FILM, AND COMPUTER READABLE STORING MEDIUM
Publication number: 20090098298Abstract: A transfer flow is produced in accordance with a process recipe of a process to be carried out. In the transfer flow, a type of modules listed in accordance with a substrate transfer order is associated with a necessary staying time from when the substrate is transferred into a module by a substrate transfer unit to when the substrate is ready to be transferred back to the substrate transfer unit after the corresponding process is finished. A cycle limiting time is determined to be the longest necessary transfer cycle time among those obtained by dividing the necessary staying time by the number of the modules mounted in the coater/developer. The number of the modules to be used is determined to be a value obtained by dividing the necessary staying time by the cycle limiting time or a nearest integer to which the value is raised.Type: ApplicationFiled: October 9, 2008Publication date: April 16, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Akira MIYATA, Masanori Tateyama -
Patent number: 6834210Abstract: A substrate-processing system has several processing units, a loading/unloading section for transferring wafers to be processed to each unit and taking out processed wafers from each unit and a sub-arm mechanism for receiving/transferring the substrates from/to the loading/unloading section and transferring the substrates one by one to each unit. The processing units and the sub-arm mechanism are controlled by a controller so that each unit processes the substrates one by one in accordance with a one-cycle time that is the maximum period among periods t1/m to tn/m obtained by dividing periods t1 to tn by the number “m” of identical units of each processing unit. The controller sets a pre-waiting time (before processing) for each processing unit.Type: GrantFiled: December 14, 2001Date of Patent: December 21, 2004Assignee: Tokyo Electron LimitedInventors: Masanori Tateyama, Akira Miyata
-
Patent number: 6526329Abstract: The present invention is a substrate processing method comprising the steps of successively extracting unprocessed wafers from a cassette, successively conveying the extracted wafers to a plurality of processing units, causing the processing units to process the wafers in parallel, and returning the processed wafers to a cassette. A process completion prediction time at which processes for one lot are completed is calculated and displayed corresponding to a process recipe that has been set to a plurality of wafers for at least one lot. Corresponding to the process completion prediction time, a cassette that contains a plurality of unprocessed wafers for one lot is accepted. A cassette that contains a plurality of processed wafers for one lot is returned.Type: GrantFiled: May 30, 2001Date of Patent: February 25, 2003Assignee: Tokyo Electron LimitedInventors: Masanori Tateyama, Syuzo Fujimaru
-
Patent number: 6507770Abstract: A system for successively extracting unprocessed substrates from a cassette, successively conveying the extracted substrates to a plurality of processing units, causing the processing units to process the substrates, and successively returning processed substrates to a cassette is disclosed. In the system, corresponding to a recipe that contains process conditions for each of at least one lot, a process start prediction time at which processes of each lot start and a process completion prediction time at which processes for each lot are completed are calculated for at least two processes. Corresponding to the process start prediction time and the process completion prediction time, at least one of optimum processing units that optimize processes for each lot is selected for each lot.Type: GrantFiled: June 6, 2001Date of Patent: January 14, 2003Assignee: Tokyo Electron LimitedInventors: Masanori Tateyama, Kenichi Okubo, Jun Ookura
-
Patent number: 6457882Abstract: A substrate processing method for forming a resist film on a wafer with a base film being formed, and performing an exposure processing and a developing processing for the resist film to thereby form a desired resist pattern, has a base reflected light analyzing step of radiating a light of the same wavelength as an exposure light radiated during the exposure processing to the base film and analyzing a reflected light, before forming the resist film, and a processing condition control step of controlling at least one of a resist film forming condition and an exposure processing condition, based on the analysis of the reflected light. The method makes it possible to control a line width of a resist pattern with high precision.Type: GrantFiled: March 13, 2001Date of Patent: October 1, 2002Assignee: Tokyo Electron LimitedInventors: Kunie Ogata, Ryouichi Uemura, Masanori Tateyama, Yoshiyuki Nakajima
-
Publication number: 20020076306Abstract: A substrate-processing system has several processing units, a loading/unloading section for transferring wafers to be processed to each unit and taking out processed wafers from each unit and a sub-arm mechanism for receiving/transferring the substrates from/to the loading/unloading section and transferring the substrates one by one to each unit. The processing units and the sub-arm mechanism are controlled by a controller so that each unit processes the substrates one by one in accordance with a one-cycle time that is the maximum period among periods t1/m to tn/m obtained by dividing periods t1 to tn by the number “m” of identical units of each processing unit. The controller sets a pre-waiting time (before processing) for each processing unit.Type: ApplicationFiled: December 14, 2001Publication date: June 20, 2002Applicant: TOKYO ELECTRON LIMITEDInventors: Masanori Tateyama, Akira Miyata
-
Patent number: 6394670Abstract: A system comprises a first maintenance interval storage for storing a first maintenance interval of each component which is not related to an actual utilization of an apparatus, a second maintenance interval storage storing a second maintenance interval of each component which is related to the actual utilization of the apparatus, a maintenance demander for demanding maintenance of some component based on the passing of the first maintenance interval of this component; and a maintenance interval prolonger for judging the second maintenance interval has passed or not based on the passing of the first maintenance interval, and when the second maintenance interval has not yet passed, suspending the demand for maintenance by the maintenance demander and prolonging the first maintenance interval. Consequently, it becomes possible to manage a maintenance timing of each component and give notice thereof on the side of the apparatus composed of a plurality of components.Type: GrantFiled: May 14, 2001Date of Patent: May 28, 2002Assignee: Tokyo Electron LimitedInventors: Kunie Ogata, Takashi Aiuchi, Masanori Tateyama
-
Publication number: 20010051837Abstract: A system for successively extracting unprocessed substrates from a cassette, successively conveying the extracted substrates to a plurality of processing units, causing the processing units to process the substrates, and successively returning processed substrates to a cassette is disclosed. In the system, corresponding to a recipe that contains process conditions for each of at least one lot, a process start prediction time at which processes of each lot start and a process completion prediction time at which processes for each lot are completed are calculated for at least two processes. Corresponding to the process start prediction time and the process completion prediction time, at least one of optimum processing units that optimize processes for each lot is selected for each lot.Type: ApplicationFiled: June 6, 2001Publication date: December 13, 2001Inventors: Masanori Tateyama, Kenichi Okubo, Jun Ookura
-
Publication number: 20010048865Abstract: The present invention is a substrate processing method comprising the steps of successively extracting unprocessed wafers from a cassette, successively conveying the extracted wafers to a plurality of processing units, causing the processing units to process the wafers in parallel, and returning the processed wafers to a cassette. A process completion prediction time at which processes for one lot are completed is calculated and displayed corresponding to a process recipe that has been set to a plurality of wafers for at least one lot. Corresponding to the process completion prediction time, a cassette that contains a plurality of unprocessed wafers for one lot is accepted. A cassette that contains a plurality of processed wafers for one lot is returned.Type: ApplicationFiled: May 30, 2001Publication date: December 6, 2001Applicant: TOKYO ELECTRON LIMITEDInventors: Masanori Tateyama, Syuzo Fujimaru
-
Publication number: 20010041076Abstract: A system comprises a first maintenance interval storage for storing a first maintenance interval of each component which is not related to an actual utilization of an apparatus, a second maintenance interval storage storing a second maintenance interval of each component which is related to the actual utilization of the apparatus, a maintenance demander for demanding maintenance of some component based on the passing of the first maintenance interval of this component; and a maintenance interval prolonger for judging the second maintenance interval has passed or not based on the passing of the first maintenance interval, and when the second maintenance interval has not yet passed, suspending the demand for maintenance by the maintenance demander and prolonging the first maintenance interval. Consequently, it becomes possible to manage a maintenance timing of each component and give notice thereof on the side of the apparatus composed of a plurality of components.Type: ApplicationFiled: May 14, 2001Publication date: November 15, 2001Applicant: TOKYO ELECTRON LIMITEDInventors: Kunie Ogata, Takashi Aiuchi, Masanori Tateyama
-
Publication number: 20010022897Abstract: A substrate processing method for forming a resist film on a wafer with a base film being formed, and performing an exposure processing and a developing processing for the resist film to thereby form a desired resist pattern, has a base reflected light analyzing step of radiating a light of the same wavelength as an exposure light radiated during the exposure processing to the base film and analyzing a reflected light, before forming the resist film, and a processing condition control step of controlling at least one of a resist film forming condition and an exposure processing condition, based on the analysis of the reflected light. The method makes it possible to control a line width of a resist pattern with high precision.Type: ApplicationFiled: March 13, 2001Publication date: September 20, 2001Applicant: TOKYO ELECTRON LIMITEDInventors: Kunie Ogata, Ryouichi Uemura, Masanori Tateyama, Yoshiyuki Nakajima
-
Publication number: 20010016225Abstract: A coating film forming apparatus comprising a coating solution supplying unit which supplies a coating solution to a rotating substrate, a memory which stores a first correlation between an atmospheric pressure and a film thickness of the coating film formed on the substrate, and a second correlation between a film thickness and a rotation speed of the substrate, an atmospheric pressure detector which detects an actual atmospheric pressure, a film thickness computation unit which computes an actual film thickness of the coating film from the actual atmospheric pressure based on the first correlation, and a rotation speed control unit which obtains a corrected rotation speed of the substrate based on the second correlation and a difference between the actual film thickness and a target film thickness, and rotate the substrate at the corrected rotation speed.Type: ApplicationFiled: February 16, 2001Publication date: August 23, 2001Inventors: Kunie Ogata, Ryoichi Uemura, Masanori Tateyama, Toshihiko Nishigaki
-
Patent number: 6054181Abstract: A method of subjecting a plurality of wafers to coating and beating treatments where a first boat is placed on a stage arranged in an interface section. The first boat is capable of containing the wafers stacked at intervals in a vertical direction. The stage is capable of moving in a horizontal direction, and has a plurality of positions for respectively placing a plurality of boats. The wafers are conveyed from a supply section to a coating section, and are subjected to a coating treatment one by one. The wafers, which have undergone the coating treatment, are conveyed to the interface section. The wafers, which have undergone the coating treatment, are loaded into the first boat placed on the stage, in the interface section. The first boat containing the wafers, which have undergone the coating treatment, is located at a transfer position by moving the stage. The first boat, located at a transfer position by moving the stage.Type: GrantFiled: August 5, 1996Date of Patent: April 25, 2000Assignees: Tokyo Electron Limited, Tokyo Electron Kyushu LimitedInventors: Mitsuhiro Nanbu, Naruaki Iida, Hideaki Gotou, Masanori Tateyama, Yuji Yoshimoto, Tomoko Ishimoto, Hidetami Yaegashi, Yasunori Kawakami, Takahide Fukuda, Akihiro Fujimoto, Takashi Takekuma, Hiroyuki Matsukawa
-
Patent number: 5725664Abstract: An apparatus for subjecting a plurality of wafers to coating and heating treatments, including a coating section for subjecting the wafers to a coating treatment one by one, a heating section for subjecting wafers which have undergone the coating treatment to a heating treatment all together, and an interface section arranged between the coating section and the heating section. The wafers are heat-treated in the heat treatment section while the wafers are stacked at intervals in a vertical direction in a boat. The wafers which have undergone the coating treatment are loaded into the boat by a conveying member in the interface section. The conveying member and the boat are surrounded by a surrounding space formed by a casing at the interface section. A circulation line is combined with an air supply and exhaust system, for circulating air in the surrounding space.Type: GrantFiled: August 5, 1996Date of Patent: March 10, 1998Assignees: Tokyo Electron Limited, Tokyo Electron Kyushu LimitedInventors: Mitsuhiro Nanbu, Naruaki Iida, Hideaki Gotou, Masanori Tateyama, Yuji Yoshimoto, Tomoko Ishimoto, Hidetami Yaegashi, Yasunori Kawakami, Takahide Fukuda, Akihiro Fujimoto, Takashi Takekuma, Hiroyuki Matsukawa
-
Patent number: 5664254Abstract: A wafer processing apparatus includes a common path, extending in a Y-axis direction, in which one wafer or a plurality of wafers are conveyed, a plurality of process units stacked on both sides of the common path to constitute multi-stage structures, a main handler moved in the common path in the Y-axis direction and rotated about a Z axis at an angle .theta.Type: GrantFiled: January 31, 1996Date of Patent: September 2, 1997Assignee: Tokyo Electron LimitedInventors: Jun Ohkura, Naruaki Iida, Hiroyuki Kudou, Masanori Tateyama, Yasuhiro Sakamoto
-
Patent number: 5565034Abstract: A substrate processing apparatus according to this invention includes an interface section having a first transfer member for transferring an object from a coating process section for applying a process solution to the object in accordance with a single sheet process to an object holding member, and a moving member for detachably supplying a plurality of object holding member and simultaneously moving the plurality of object holding member, and a heat-treatment section having a second transfer member for transferring the object placed on the object holding member to a heat-treatment section for heat-treating the plurality of objects, which have undergone the coating process, in accordance with a batch process.Type: GrantFiled: October 28, 1994Date of Patent: October 15, 1996Assignees: Tokyo Electron Limited, Tokyo Electron Kyushu LimitedInventors: Mitsuhiro Nanbu, Naruaki Iida, Hideaki Gotou, Masanori Tateyama, Yuji Yoshimoto, Tomoko Ishimoto, Hidetami Yaegashi, Yasunori Kawakami, Takahide Fukuda, Akihiro Fujimoto, Takashi Takekuma, Hiroyuki Matsukawa
-
Patent number: RE37470Abstract: A wafer processing apparatus includes a common path, extending in a Y-axis direction, in which one wafer or a plurality of wafers are conveyed, a plurality of process units stacked on both sides of the common path to constitute multi-stage structures, a main handler moved in the common path in the Y-axis direction and rotated about a Z axis at an angle &thgr; to load/unload the wafer into/from the process units, an arm section arranged to move in the main handler in the Z-axis direction, a plurality of holding arms arranged in the arm section to constitute a multi-stage structure so as to respectively hold the wafers, each holding arm being advanced and retreated on an X-Y plane from the arm section, an optical sensor, arranged in the arm section, for detecting a holding state of the wafer in each of the plurality of holding arms, and a controller for controlling an operation of the main handler, an operation of the arm section, and operations of the plurality of holding arms on the basis of a detection resulType: GrantFiled: September 2, 1999Date of Patent: December 18, 2001Assignee: Tokyo Electron LimitedInventors: Jun Ohkura, Naruaki Iida, Hiroyuki Kudou, Masanori Tateyama, Yasuhiro Sakamoto