Abstract: An optical fiber bundle structure includes: plural optical fiber core wires; a crossing preventing member; and a grasping member. Further, the crossing preventing member has slits and the widths of the slits positioned at the respective sides are each equal to or larger than a difference between: a length of one side of a polygon circumscribing the plural optical fiber core wires at a hindmost end portion of the slits at the trailing end; and a length of one side of a polygon circumscribing the plural optical fiber core wires at the leading end.

Abstract: An optical fiber bundle structure includes: plural optical fiber core wires; a crossing preventing member; and a grasping member. Further, the crossing preventing member has slits and the widths of the slits positioned at the respective sides are each equal to or larger than a difference between: a length of one side of a polygon circumscribing the plural optical fiber core wires at a hindmost end portion of the slits at the trailing end; and a length of one side of a polygon circumscribing the plural optical fiber core wires at the leading end.

Abstract: Semiconductor devices and multiply-accumulate operation devices are disclosed. In one example, a semiconductor device includes synapses in which a nonvolatile variable resistance element taking a first resistance value and a second resistance value lower than the first resistance value and a fixed resistance element having a resistance value higher than the second resistance value are connected in series. An output line outputs a sum of currents flowing through the plurality of synapses.

Abstract: An optical fiber bundle structure includes: plural optical fiber core wires; a crossing preventing member; and a grasping member. Further, the crossing preventing member has slits and the widths of the slits positioned at the respective sides are each equal to or larger than a difference between: a length of one side of a polygon circumscribing the plural optical fiber core wires at a hindmost end portion of the slits at the trailing end; and a length of one side of a polygon circumscribing the plural optical fiber core wires at the leading end.

Abstract: A cable includes a cable core including one or more electric wires, a shield layer covering around the cable core, and a sheath covering around the shield layer. The shield layer is composed of a braided shield including a plurality of first metal wires composed of aluminum or aluminum alloy and a plurality of second metal wires composed of copper or copper alloy. The plurality of first metal wires and the plurality of second metal wires are cross-braided.

Abstract: A multiply-accumulate operation device according to an aspect of the present disclosure includes multiple cells each including a transistor and a ferroelectric capacitor that is coupled to a first source and drain terminal of the transistor. The multiple cells are arranged in rows and columns. This multiply-accumulate operation device further includes multiple input wiring lines and multiple output wiring lines. Each unit of one or more of the multiple input wiring lines is assigned to corresponding one of the rows of the multiple cells. The multiple input wiring lines are coupled to the ferroelectric capacitors. Each of the multiple output wiring lines is assigned to corresponding one of the columns of the multiple cells. The multiple output wiring lines are coupled to second source and drain terminals of the transistors.

Abstract: A semiconductor storage device and an electronic device that include a ferroelectric capacitor having a more optimized structure, as a memory cell are provided. A semiconductor storage device includes a field-effect transistor provided in an active region of a semiconductor substrate, a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field-effect transistor, a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor, and a bit line electrically connected to another one of the source or the drain of the field-effect transistor, in which a gate electrode of the field-effect transistor extends in a first direction across the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction.

Abstract: There is provided a semiconductor storage device that is allowed to obtain a sufficient margin for operation. The semiconductor storage device includes: a field-effect transistor; an interlayer insulating film; a contact; a first wiring layer; a first insulating layer; an opening section; and a ferroelectric capacitor. The field-effect transistor is provided in a semiconductor substrate. The interlayer insulating film is provided on the semiconductor substrate. The contact penetrates the interlayer insulating film and is electrically coupled to a drain of the field-effect transistor. The first wiring layer is provided on the contact. The first insulating layer is provided on the interlayer insulating film and has the first wiring layer buried therein. The opening section is provided in the first insulating layer and the interlayer insulating film from a layer upper than the first wiring layer.

Abstract: A product-sum calculation with high power efficiency is performed while maintaining a small area of a memory cell. A semiconductor device includes a memory cell array in which a plurality of memory cells is arranged in a matrix.

Abstract: [Object] To provide a semiconductor element capable of realizing an element having a nonvolatile memory capable of stably storing highly integrated data, a nonvolatile memory device, a multiply-accumulate operation device, and a method of manufacturing the semiconductor element. [Solving means] A semiconductor element according to an embodiment of the present technology includes a plurality of cell blocks. The plurality of cell blocks are configured by connecting a plurality of cell portions in series with each other, the plurality of cell portions each having a MOSFET for controlling conduction of a channel portion and a resistor connected in parallel to the channel portion, and configured to store data by a resistance level set for each of the plurality of cell portions.

Abstract: A semiconductor device according to an embodiment of the present technology includes a plurality of first wires, a plurality of second wires, a plurality of third wires, and a plurality of memory units. The plurality of first wires is arranged to be parallel to each other. The plurality of second wires is arranged to be parallel and adjacent to the plurality of first wires, respectively. The plurality of third wires is arranged to be orthogonal to the first wires and the second wires. The plurality of memory units each has a nonvolatile memory layer that maintains a state set via the third wire, and an active layer that is arranged obliquely to the third wire and electrically connects the first wire and the second wire adjacent to each other in accordance with the state of the memory layer and is a MOSFET-type.

Abstract: To provide a semiconductor storage apparatus, a product-sum calculation apparatus, and electronic equipment in which memory cells are highly integrated and highly densified. A semiconductor storage apparatus including: a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions; and a second transistor including source or drain regions in an activation layer provided on the first gate electrode and a second gate electrode on the activation layer via an insulating film.

Abstract: Provided is a semiconductor storage device and an electronic apparatus having a structure that is more suitable for miniaturization and high integration of memory cells. A semiconductor storage device includes: a recessed portion provided in a semiconductor substrate; a ferroelectric film provided along an inner side of the recessed portion; an electrode provided on the ferroelectric film so as to be embedded in the recessed portion; a first conductivity-type separation region provided in the semiconductor substrate under the recessed portion; and a second conductivity-type electrode region provided in the semiconductor substrate on at least one side of the recessed portion.

Abstract: Provided are a semiconductor storage element, a semiconductor device, an electronic device, and a manufacturing method of a semiconductor storage element that enable higher-speed operations. The semiconductor storage element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type that is provided below the first semiconductor layer; a gate electrode provided on the first semiconductor layer; a gate insulator film provided between the first semiconductor layer and the gate electrode; a drain region of the second conductivity type that is provided in the first semiconductor layer on one side of the gate electrode; a source region of the second conductivity type that is provided in the first semiconductor layer on another side facing the one side across the gate electrode; and a bit line configured to electrically connect with both of the source region and the first semiconductor layer.

Abstract: To provide a semiconductor memory device that avoids a voltage drop caused by an oxide film formed on a surface of a semiconductor substrate, and appropriately operates even in a case where a memory cell array is formed. A semiconductor memory device including a first transistor, a capacitor provided with a pair of capacitor electrodes opposed to each other via an insulator, one of the capacitor electrodes being electrically coupled to a gate electrode of the first transistor, a second transistor in which one of a source or a drain is electrically coupled to one of a source or a drain of the first transistor and to another of the capacitor electrodes, and a plate line electrically coupled to the gate electrode of the first transistor and to the one of the capacitor electrodes.

Abstract: Provided is a semiconductor storage element including a first transistor having a gate insulation film that includes a ferroelectric material at least partially and being a transistor to which information is written, and a second transistor that is coupled to, at one of a source and a drain, a source or drain of the first transistor. The first transistor has a threshold voltage smaller than 0 V when writing information and a threshold voltage smaller than 0 V when erasing information.

Abstract: A Provided is a semiconductor storage element that includes a memory cell transistor including a gate insulator film at least partially including ferroelectric material, and a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer.

Abstract: [Overview] [Problem to be Solved] To provide a non-volatile semiconductor memory that is capable of high-speed writing or reading and suitable for high-density integration. [Solution] A semiconductor device including: a first inverting circuit including n-type FET and p-type FET; a second inverting circuit including n-type FET and p-type FET; a first ferroelectric capacitor; a second ferroelectric capacitor; and a plate line. The second inverting circuit has an output coupled to an input of the first inverting circuit and has an input coupled to an output of the first inverting circuit. The first ferroelectric capacitor has one of electrodes coupled to the input of the first inverting circuit. The second ferroelectric capacitor has one of electrodes coupled to the input of the second inverting circuit. The plate line is coupled to another of the electrodes of the first ferroelectric capacitor and another of the electrodes of the second ferroelectric capacitor.

Abstract: To provide a semiconductor storage apparatus, a product-sum calculation apparatus, and electronic equipment in which memory cells are highly integrated and highly densified. A semiconductor storage apparatus including: a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions; and a second transistor including source or drain regions in an activation layer provided on the first gate electrode and a second gate electrode on the activation layer via an insulating film.

Abstract: [Problem] Provided are a semiconductor device and a multiply-accumulate operation device that enable integration at a higher density by further reducing a mounting area per synapse. [Solution] A semiconductor device including: a plurality of synapses in which a nonvolatile variable resistance element taking a first resistance value and a second resistance value lower than the first resistance value and a fixed resistance element having a resistance value higher than the second resistance value are connected in series; and an output line that outputs a sum of currents flowing through the plurality of synapses. [Selected Drawing] FIG.