Abstract: Provided is a semiconductor device that is easily controlled. The semiconductor device includes a first switching device and a second switching device that are connected in series between a first potential and a second potential lower than the first potential, wherein each of the first and second switching devices includes a transistor region, and a diode region electrically connected in anti-parallel to the transistor region, the transistor region includes a first gate controlled by a first gate signal, and the diode region includes a diode gate controlled by a diode gate signal.

Abstract: A semiconductor device includes a field insulating film formed on an epitaxial layer, a front surface electrode covering an inner peripheral end of the field insulating film, and an outer peripheral electrode covering an outer peripheral end of the field insulating film. In a surface layer portion of the epitaxial layer, a termination well region that is connected to the front surface electrode and extends to the outside of an outer peripheral end of the front surface electrode is formed. The semi-insulating film is formed so as to cover a part of the field insulating film apart from the front surface electrode and the outer peripheral electrode. The semi-insulating film is connected to the epitaxial layer through an opening formed in the field insulating film in each of a region inside and a region outside an outer peripheral end of the termination well region.

Abstract: A first principal electrode and a first control electrode pad are formed on a first principal surface of the semiconductor chip. A second principal electrode and a second control electrode pad are formed on a second principal surface of the semiconductor chip. The second principal electrode and the second control electrode pad are respectively bonded to first and second metal patterns of an insulating substrate. Bonding sections of first and second wires overlap a bonding section of the second principal electrode or the second control electrode pad in plan view. Thickness of the first and second metal patterns is 0.2 mm or less.

Abstract: A semiconductor device according to the present disclosure includes a P layer, an insulating film, an electrode, a plurality of P- layers arranged on a side of a termination region of the P layer, an N- layer, an N++ layer, an insulating film, an electrode, a high permittivity layer disposed at least on the P- layers, and a low permittivity layer disposed on the high permittivity layer, and a distance between an end on a side of an active region of the insulating film and an end on a side of the termination region of one of the P- layers located farthest from the active region is more than µm and µm or less, and a distance between the end on the side of the active region of the insulating film and an end on a side of the active region of the electrode is 50 µm or more.

Abstract: When a positive gate voltage is applied to a first one of a first gate electrode and a second gate electrode, and current flows from a collector electrode to an emitter electrode, a semiconductor device applies a positive gate voltage to a second one of the first gate electrode and the second gate electrode. When a positive gate voltage is applied to the first one and current flows from the emitter electrode to the collector electrode, the semiconductor device applies voltage equal to or less than reference voltage to the second one.

Abstract: A state estimation system for a power conversion semiconductor apparatus in an embodiment includes an analysis processing unit and an estimation processing unit. The analysis processing unit projects points indicating a combination of a voltage detection value in first time history data of a voltage between the pair of main terminals detected when the pair of main terminals are forward-biased and when the pair of main terminals are reverse-biased and a current detection value in second time history data of detection values of both a forward current and a reverse current between the pair of main terminals onto a coordinate plane including a voltage axis and a current axis on the basis of the first time history data and the second time history data in the power conversion semiconductor apparatus including the pair of main terminals and derives a distribution of the projected points on the coordinate plane.

Abstract: A method for fabricating a high-voltage insulated gate type bipolar semiconductor device by comparing to a reference structure of the same includes determining a width S of a mesa region in which the gate insulating film and the MOS transistor are formed, and a trench depth DT, based on a scaling ratio K, in comparison with a second width and a second trench depth of the reference structure, and setting a cell width 2W of the high-voltage insulated gate type bipolar semiconductor device to be equal in length to a second length of the reference structure, the scaling ratio K being defined as K=Y/X, where X indicates a size of a target portion to be miniaturized in the high-voltage insulated gate type bipolar semiconductor device, and Y indicates a size of a target portion to be miniaturized in the reference structure.

Abstract: A method for fabricating a high-voltage insulated gate type bipolar semiconductor device by comparing to a reference structure of the same includes determining a width S of a mesa region in which the gate insulating film and the MOS transistor are formed, and a trench depth DT, based on a scaling ratio K, in comparison with a second width and a second trench depth of the reference structure, and setting a cell width 2W of the high-voltage insulated gate type bipolar semiconductor device to be equal in length to a second length of the reference structure, the scaling ratio K being defined as K=Y/X, where X indicates a size of a target portion to be miniaturized in the high-voltage insulated gate type bipolar semiconductor device, and Y indicates a size of a target portion to be miniaturized in the reference structure.

Abstract: A high-voltage insulated gate type power semiconductor device includes a low-concentration first conductivity type base layer; a plurality of trenches selectively formed with large intervals and narrow intervals provided alternately, in a front surface of the low-concentration first conductivity type base layer; a gate insulating film formed on a surface of each of the plurality of trenches; a gate electrode formed inside the gate insulating film; and a second conductivity type base layer selectively formed between the adjacent trenches sharing the narrow interval. The high-voltage insulated gate type power semiconductor device includes a high-concentration first conductivity type source layer selectively formed on a front surface of the second conductivity type base layer.

Abstract: A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer.

Abstract: A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer.

Abstract: A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.

Abstract: In a vertical semiconductor device including a first base layer of a first conductivity type, second base layers of a second conductivity type, emitter layer of the first conductive type and gate electrodes which are formed at one main surface of the first base layer and including a buffer layer of the first conductivity type, a collector layer of the second conductivity type and a collector electrode which are formed at the other main surface of the first base layer, an electric field relaxing structure selectively formed outside from the second base layers and the collector layer is formed expect the region below the electric field relaxing structure.

Abstract: A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.

Abstract: A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer.

Abstract: A support mechanism includes a support member which has a tab slidable along a groove, and can be fixed at a desired position when an engagement teeth array in the tab engages with an engagement hook. Also, a pressing member with a presser portion is movable along the engagement teeth array, and can be fixed at a desired position when an engagement hook engages with an engagement teeth array. Thus, a single front panel can be used for a number of flat display panels of different sizes.

Abstract: A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.

Abstract: In a vertical semiconductor device including a first base layer of a first conductivity type, second base layers of a second conductivity type, emitter layer of the first conductive type and gate electrodes which are formed at one main surface of the first base layer and including a buffer layer of the first conductivity type, a collector layer of the second conductivity type and a collector electrode which are formed at the other main surface of the first base layer, an electric field relaxing structure selectively formed outside from the second base layers and the collector layer is formed expect the region below the electric field relaxing structure.

Abstract: A support mechanism (A) includes a support member (4) which has a tab (4d) slidable along a groove (3a), and can be fixed at a desired position when an engagement teeth array (7) in the tab (4d) engages with an engagement hook (3b). Also, a pressing member (5) with a presser portion (5c) is movable along the engagement teeth array (6), and can be fixed at a desired position when an engagement hook (5d) engages with an engagement teeth array (6). Thus, a single front panel (1) can be used for a number of flat display panels of different sizes.

Abstract: A mounting structure for attaching a display panel (200) to a cover (100) of a display, comprising: a plurality of attaching portions (210) provided at a circumference of the display panel (200), each of the attaching portions including a screw hole penetrating thicknesswise of the display panel (200) and also including a guide wall formed on the surface of the display panel (200) facing the cover (100), the guide wall (230) surrounding the screw hole and extending thicknesswise of the display panel (200); and a plurality of bosses (300) vertically formed at the cover (100) and extending thicknesswise of the display panel (200), corresponding to a respective one of the attaching portions (210) for receiving screws, each of the bosses (300) integrally formed with at least two guide members (330, 340) that elastically contact the guide wall (230) and elastically deformed in a direction across an axis of the boss (300); wherein when the guide members (330, 340) of each of the bosses (300) come into elastic conta