Patents by Inventor Masao Asai

Masao Asai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8052856
    Abstract: A support for capillaries comprises a ceramic member having a flat surface area on which the capillaries are to be aligned. The flat surface area has a flatness of not more than 0.02 mm and has a mean spacing of waviness motifs (AW) of not more than 100 ?m.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: November 8, 2011
    Assignee: Kyocera Corporation
    Inventors: Masao Asai, Masahiro Okumura, Yoshihiro Okawa
  • Publication number: 20080171178
    Abstract: A support for capillaries comprises a ceramic member having a flat surface area on which the capillaries are to be aligned. The flat surface area has a flatness of not more than 0.02 mm and has a mean spacing of waviness motifs (AW) of not more than 100 ?m.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 17, 2008
    Applicant: KYOCERA CORPORATION
    Inventors: Masao ASAI, Masahiro OKUMURA, Yoshihiro OKAWA
  • Patent number: 6829681
    Abstract: A dual system includes a 0-subsystem and a 1-subsystem, each of which in turn includes a first bus, a second bus, a main memory having a memory section reading from and writing into which is performed over the first bus, a cache memory, a processor for outputting a first command for instruction to write back data of the cache memory into the main memory, a cache memory control section having a first reset terminal, through which an element thereof takes part in control of the first bus, for performing write back processing of data of the cache memory into the main memory based on the first command, and a system control section for controlling system changeover between an act system and a standby system over the system confounding line.
    Type: Grant
    Filed: June 7, 2000
    Date of Patent: December 7, 2004
    Assignee: Fujitsu Limited
    Inventor: Masao Asai
  • Patent number: 6705770
    Abstract: In an opto-electronic module including an opto-electronic unit and a receptacle, the receptacle has an outer indentation. When the module is assembled, the receptacle is held in a fixture with a projecting lip that fits into the indentation. After optical alignment, the receptacle is fastened to the opto-electronic unit by welding. The projecting lip prevents the receptacle from moving during the welding process, thereby assuring that optical alignment is maintained.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: March 16, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Masao Asai
  • Publication number: 20030142927
    Abstract: In an opto-electronic module including an opto-electronic unit and a receptacle, the receptacle has an outer indentation. When the module is assembled, the receptacle is held in a fixture with a projecting lip that fits into the indentation. After optical alignment, the receptacle is fastened to the opto-electronic unit by welding. The projecting lip prevents the receptacle from moving during the welding process, thereby assuring that optical alignment is maintained.
    Type: Application
    Filed: January 30, 2002
    Publication date: July 31, 2003
    Inventor: Masao Asai
  • Patent number: 5402430
    Abstract: A parity inversion test system includes an interface part having an input side coupled to a N-bit data line and an output side coupled to a M-bit data line, where N<M, an output coupling part for coupling at least a part of a data output from the output side of the interface part to the data output from the output side of the interface part in a test mode so as to output a M-bit data, a parity generating part for generating a parity data with respect to the M-bit data output to the M-bit data line via the output coupling part based on the M-bit data, and a parity inversion bit specifying part for specifying arbitrary bits of the M-bit data output to the M-bit data line which are to be inverted when generating the parity data in the parity generating part.
    Type: Grant
    Filed: October 2, 1992
    Date of Patent: March 28, 1995
    Assignee: Fujitsu Limited
    Inventors: Masao Asai, Yuji Shibata, Makoto Okazaki