Abstract: A semiconductor integrated circuit is configured which has a logic circuit having scan path flip-flops and a test circuit which executes a scan path test. The test circuit includes a clock control circuit and a scan enable control signal generation circuit. The scan enable control signal generation circuit receives a clock-on information signal output from the clock control circuit and supplies a scan enable control signal to another clock control circuit. The other clock control circuit identifies the value of a scan enable signal on the basis of the scan enable control signal. At this time, the scan path flip-flops output fixed values from data output terminals according to the value of the scan enable signal.

Abstract: In a method of designing a test facile semiconductor integrated circuit with scan paths, a method of designing an optimum assigning arrangement of scan paths. For minimizing an area of interconnection wiring of scan paths among the logic blocks, the average number of flip-flops to be subjected to a scan path test, expressed another word as a scan path length, is calculated at first. Combinations and division of the logic blocks on which a scan path is assigned are calculated for all number of scan paths. Wiring length of interconnection among the logic blocks for each assigning combination of total scan paths is calculated to select the shortest wiring length interconnection among logic blocks as the optimal scan paths assigning arrangement.