Patents by Inventor Masao Iruka

Masao Iruka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090212811
    Abstract: A method for testing a semiconductor device having plural transmitting (TX) circuits and plural receiving (RX) circuits at a low cost and in a short time. The semiconductor device includes two or more pairs of transmitting and receiving circuits. Each of the transmitting circuits converts parallel data to serial data and transmits the converted serial data to external while each of the receiving circuits receives serial data from external and converts the received serial data to parallel data. Furthermore, the semiconductor device includes a device that enables two or more selected pairs of transmitting and receiving circuits to be connected serially and alternately. The semiconductor device can be configured so that the serially connected transmitting or receiving circuit in the first stage inputs a test signal to be compared with a signal output from the serially connected receiving or transmitting circuit in the last stage.
    Type: Application
    Filed: February 18, 2009
    Publication date: August 27, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Masao Iruka
  • Patent number: 5422441
    Abstract: In a master slice integrated circuit, a number of connection pads are located in a peripheral edge region of a chip in such a manner that each one power supply pad is interposed between each pair of signal input/output pads and a number of unitary pad arrays each of which consists of a signal pad, a power supply pad and another signal pad located in the named order are repeatedly arranged along a peripheral edge of the chip. Thus, the pad pitch can be reduced to two thirds of the width of an I/O cell, without changing the I/O cell size. In addition, since the power supply pad is located adjacent each of the I/O cells, it is effective to suppress or minimize the power supply voltage noise caused by the simultaneous driving.
    Type: Grant
    Filed: April 1, 1993
    Date of Patent: June 6, 1995
    Assignee: NEC Corporation
    Inventor: Masao Iruka