Abstract: A calibration device for a non-destructive inspection/measurement system is provided, including an excitation coil; a detection coil; and a computer that applies a sinusoidal signal or a combined signal including multiple sinusoids having mutually different frequencies to the excitation coil in order to excite a pipe body, and that detects changes in the output voltage of the detection coil. The calibration device calibrates the detection results in the computer by entering, as variables in simultaneous equations, the amplitudes and phase differences of the output voltage of the detection coil at multiple calibration points of known thickness on the pipe body. The calibration device performs calibrations by using multiple different calibration conditions at each of the calibration points, and entering, into the simultaneous equations, the amplitudes and phase differences of the output voltage of the detection coil for each of the calibration conditions.

Abstract: A calibration device for a non-destructive inspection/measurement system is provided, including an excitation coil; a detection coil; and a computer that applies a sinusoidal signal or a combined signal including multiple sinusoids having mutually different frequencies to the excitation coil in order to excite a pipe body, and that detects changes in the output voltage of the detection coil. The calibration device calibrates the detection results in the computer by entering, as variables in simultaneous equations, the amplitudes and phase differences of the output voltage of the detection coil at multiple calibration points of known thickness on the pipe body. The calibration device performs calibrations by using multiple different calibration conditions at each of the calibration points, and entering, into the simultaneous equations, the amplitudes and phase differences of the output voltage of the detection coil for each of the calibration conditions.

Abstract: Techniques for arranging ball grid arrays for producing low thermal resistance packages. One embodiment is for a ball grid array package that comprises a substrate, the substrate having a top surface and a bottom surface. A plurality of thermal balls are coupled to the bottom surface of the substrate, and at least one vias is positioned between every pair of the plurality of thermal balls. Other embodiments contemplate a ball grid array comprising thermal balls with a via located between every four thermal balls, wherein at least one vias is substituted for a thermal ball in the ball grid array.

Abstract: A system and method for synchronizing a system clock in accordance with a program clock reference of a content data stream includes application of incremental delays to a local clock signal having a higher frequency than that specified by the program clock reference. The delay is made over a period defined by phase comparison between a system clock signal and a minimum delay value. Delay values are incremented proportionally to a number of clock cycles over the period. The subject system allows for display of jitter free audio or video decoded from the content data stream, and is realized in circuitry that is readily implement on an integrated circuit.

Abstract: A digitally controlled delay line generates a clock signal. The clock signal can be modulates as a spread spectrum clock signal. In an example embodiment, the programmable delay line has an input for receiving a signal, an output that delays outputting the input signal by a time period programmed into a delay value input. A feedback loop comprising an inverter is coupled between the input and the output of the programmable delay line.

Abstract: A system and method for synchronizing a system clock in accordance with a program clock reference of a content data stream includes application of incremental delays to a local clock signal having a higher frequency than that specified by the program clock reference. The delay is made over a period defined by phase comparison between a system clock signal and a minimum delay value. Delay values are incremented proportionally to a number of clock cycles over the period. The subject system allows for display of jitter free audio or video decoded from the content data stream, and is realized in circuitry that is readily implement on an integrated circuit.

Abstract: A digitally controlled delay line generates a clock signal. The clock signal can be modulates as a spread spectrum clock signal. In an example embodiment, the programmable delay line has an input for receiving a signal, an output that delays outputting the input signal by a time period programmed into a delay value input. A feedback loop comprising an inverter is coupled between the input and the output of the programmable delay line.

Abstract: A charge pump that employs a differential amplifier that provides a differential output to control a charge up current source and a charge down current source. The differential amplifier is configured so that the current sources can maintain substantially equal charge up current and charge down current irrespective of the voltage at its output terminal.

Abstract: A clock signal generator varies a frequency of a digital clock over a selected range of frequencies. The generator employs a divider for lowering a frequency of a clock signal. A counter increments synchronously with the signal, and causes a selected sequence of outputs to be generated by a pattern generator. The pattern generator output forms an input to a digitally controllable delay line which receives the lower frequency clock signal. The pattern generator causes the digital delay line to vary a frequency of the lowered frequency clock signal between selected boundaries. The varying frequency clock signal is then raised up again such that a final clock has a varying frequency, and will exhibit less EMI spiking during switching of an associated, synchronous digital data device. The solid state nature of the generator allows for simple fabrication, inexpensive manufacture and ready integration into digital circuitry, such as multifunction integrated circuits.

Abstract: A clock signal generator varies a frequency of a digital clock over a selected range of frequencies. The generator employs a divider for lowering a frequency of a clock signal. A counter increments synchronously with the signal, and causes a selected sequence of outputs to be generated by a pattern generator. The pattern generator output forms an input to a digitally controllable delay line which receives the lower frequency clock signal. The pattern generator causes the digital delay line to vary a frequency of the lowered frequency clock signal between selected boundaries. The varying frequency clock signal is then raised up again such that a final clock has a varying frequency, and will exhibit less EMI spiking during switching of an associated, synchronous digital data device. The solid state nature of the generator allows for simple fabrication, inexpensive manufacture and ready integration into digital circuitry, such as multifunction integrated circuits.

Abstract: A real time clock that operates an oscillator within a predetermined range by employing a constant current source. The remaining real time clock logic can be operated at a voltage that is relative to the constant current. Power consumption of the oscillator can be controlled by limiting the current from the constant current source. The outputs of the oscillator can be input into a signal detector. A clocking signal can be produced by the signal detector based on the oscillator signals. The current provided by the first current source is limited to provide low power operation of the oscillator. Optionally, the signal detector can employ a differential amplifier. The differential amplifier receives the oscillator outputs, and provides a clocking signal based on the oscillator outputs.

Abstract: A technique for generating multiple clock signals using a frequency generator for generating a common clock signal. A first digital divider and multiplier receives the common clock signal and produces a first clock signal. A second digital divider and multiplier receives the common clock signal and produces a second clock signal, the second clock signal being at a different frequency than the first clock signal. A third digital divider and multiplier receives the common clock signal and produces a third clock signal, the third clock signal being at a different frequency than the first clock signal and the second clock signal. The common clock signal can be the greatest common measure of the first, second and third clock signals divided by a multiple of two.

Abstract: Techniques for arranging ball grid arrays for producing low thermal resistance packages. One embodiment is for a ball grid array package that comprises a substrate, the substrate having a top surface and a bottom surface. A plurality of thermal balls are coupled to the bottom surface of the substrate, and at least one vias is positioned between every pair of the plurality of thermal balls. Other embodiments contemplate a ball grid array comprising thermal balls with a via located between every four thermal balls, wherein at least one vias is substituted for a thermal ball in the ball grid array.

Abstract: A clock signal generator varies a frequency of a digital clock over a selected range of frequencies. The generator employs a divider for lowering a frequency of a clock signal. A counter increments synchronously with the signal, and causes a selected sequence of outputs to be generated by a pattern generator. The pattern generator output forms an input to a digitally controllable delay line which receives the lower frequency clock signal. The pattern generator causes the digital delay line to vary a frequency of the lowered frequency clock signal between selected boundaries. The varying frequency clock signal is then raised up again such that a final clock has a varying frequency, and will exhibit less EMI spiking during switching of an associated, synchronous digital data device. The solid state nature of the generator allows for simple fabrication, inexpensive manufacture and ready integration into digital circuitry, such as multifunction integrated circuits.

Abstract: A real time clock that operates an oscillator within a predetermined range by employing a constant current source. The remaining real time clock logic can be operated at a voltage that is relative to the constant current. Power consumption of the oscillator can be controlled by limiting the current from the constant current source. The outputs of the oscillator can be input into a signal detector. A clocking signal can be produced by the signal detector based on the oscillator signals. The current provided by the first current source is limited to provide low power operation of the oscillator. Optionally, the signal detector can employ a differential amplifier. The differential amplifier receives the oscillator outputs, and provides a clocking signal based on the oscillator outputs.

Abstract: A technique for generating multiple clock signals using a frequency generator for generating a common clock signal. A first digital divider and multiplier receives the common clock signal and produces a first clock signal. A second digital divider and multiplier receives the common clock signal and produces a second clock signal, the second clock signal being at a different frequency than the first clock signal. A third digital divider and multiplier receives the common clock signal and produces a third clock signal, the third clock signal being at a different frequency than the first clock signal and the second clock signal. The common clock signal can be the greatest common measure of the first, second and third clock signals divided by a multiple of two.

Abstract: A charge pump that employs a differential amplifier that provides a differential output to control a charge up current source and a charge down current source. The differential amplifier is configured so that the current sources can maintain substantially equal charge up current and charge down current irrespective of the voltage at its output terminal.

Abstract: A clock signal generator varies a frequency of a digital clock over a selected range of frequencies. The generator employs a divider for lowering a frequency of a clock signal. A counter increments synchronously with the signal, and causes a selected sequence of outputs to be generated by a pattern generator. The pattern generator output forms an input to a digitally controllable delay line which receives the lower frequency clock signal. The pattern generator causes the digital delay line to vary a frequency of the lowered frequency clock signal between selected boundaries. The varying frequency clock signal is then raised up again such that a final clock has a varying frequency, and will exhibit less EMI spiking during switching of an associated, synchronous digital data device. The solid state nature of the generator allows for simple fabrication, inexpensive manufacture and ready integration into digital circuitry, such as multifunction integrated circuits.

Abstract: A circuit has a logic memory, a preceding logic circuit, a succeeding logic circuit, and a function defining circuit. An input signal is taken by the preceding logic circuit, where a new logic state is produced based on the input signal and a present logic state in the logic memory executing a defined calculation. The content of the logic memory is taken over by the new logic state. The succeeding logic circuit produces an output signal based on the logic state of the logic memory executing a defined calculation. The calculation executed in the succeeding or preceding logic circuit is defined by the defining function circuit. Thus, the whole circuit operates with a desired function.

Abstract: An electronic timepiece comprises an oscillator, a frequency divider for frequency dividing the output signal of the oscillator to generate 100 Hz output pulse signals, time count circuits having a plurality of counters cascade-connected to count the output pulse signals of the frequency divider, a decoder circuit for decoding the output signal of the time count circuits to generate a display signal and a display device for displaying data corresponding to the output display signal of the decoder circuit, in which a stopwatch display mode and a normal time display mode may be selected by the operation of a switch. The electronic timepiece further includes a control circuit connected between the decoder circuit and display device and adapted to inhibit normal time display data from being supplied to the display device in response to the operation of the switch which sets the electronic timepiece into the stopwatch display mode.