Abstract: A semiconductor memory device comprising a substrate, a longitudinal source diffusion layer for a plurality of memory transistor source regions continuously formed on the substrate, and a longitudinal drain diffusion layer for a plurality of memory transistor drain regions continuously formed on the substrate in parallel to the source diffusion layer. A word line is formed crossing over the diffusion layers. And an electrically insulating film is interposed between the word line and the diffusion layers. The insulating film is thicker than a gate oxide film formed between the diffusion layers.

Abstract: A memory cell array has a continuous diffusion region for source regions of a plurality of memory transistors; a continuous diffusion region for drain regions of the plurality of memory transistors; the both diffusion regions being formed in a substrate in parallel to each other; and word lines electrically insulated from the both diffusion regions and formed in a direction crossing the both diffusion regions; the word lines being composed of polycrystal silicon films in first and second layers and alternately arranged and electrically insulated from each other. A region of the memory transistors for ion implantation is wider than a channel region of the memory transistors. The region of the memory transistors for ion implantation is formed up to the channel region of the memory cell transistors provided by the word lines in the second layer. A thick oxide film is formed on the both diffusion regions.