Patents by Inventor Masao Kumagai
Masao Kumagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8823344Abstract: A control circuit arranged in a power supply including first and second switches to control an output voltage of the power supply. The control circuit includes a first control circuit that switches the first and second switches in a complementary manner in accordance with a comparison result of a first reference voltage and a feedback voltage corresponding to the output voltage of the power supply. A first comparison circuit compares the output voltage or feedback voltage with a second reference value. A second comparison circuit compares a coupling point current flowing through a coupling point between the first and second switches with a third reference value. A second control circuit disables complementary switching of the first and second switches in accordance with an output signal from the first comparison circuit and enables the complementary switching in accordance with an output signal of the second comparison circuit.Type: GrantFiled: December 16, 2011Date of Patent: September 2, 2014Assignee: Spansion LLCInventors: Koichiro Kushida, Kazuyoshi Futamura, Masao Kumagai
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Patent number: 8518543Abstract: A sliding member is produced by forming hardening layers with two-layered structure on surface of a substrate metal with a Vickers hardness of not more than Hv300, such as aluminum or magnesium alloy for example, and then forming a DLC film having surface roughness defined as maximum height roughness Rz of 1 to 10 ?m further on the hardening layers. The above-described hardening layers are composed of a first hardening layer dispersed with heavy metal particles, preferably made of tungsten and/or tantalum in the substrate metal, and a second hardening layer formed under the first hardening layer.Type: GrantFiled: February 3, 2009Date of Patent: August 27, 2013Assignees: FujiWPC Co., Ltd., Fuji Kihan Co., Ltd.Inventors: Makoto Kano, Takahiro Horiuchi, Shinichi Takagi, Masao Kumagai, Eiji Shimodaira, Yoshio Miyasaka
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Publication number: 20120212195Abstract: A control circuit arranged in a power supply including first and second switches to control an output voltage of the power supply. The control circuit includes a first control circuit that switches the first and second switches in a complementary manner in accordance with a comparison result of a first reference voltage and a feedback voltage corresponding to the output voltage of the power supply. A first comparison circuit compares the output voltage or feedback voltage with a second reference value. A second comparison circuit compares a coupling point current flowing through a coupling point between the first and second switches with a third reference value. A second control circuit disables complementary switching of the first and second switches in accordance with an output signal from the first comparison circuit and enables the complementary switching in accordance with an output signal of the second comparison circuit.Type: ApplicationFiled: December 16, 2011Publication date: August 23, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Koichiro Kushida, Kazuyoshi Futamura, Masao Kumagai
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Patent number: 7978168Abstract: A D/A converter for receiving a plurality of divisional voltages and converting a digital signal to an analog voltage with the divisional voltages, the D/A converter includes a selection circuit for receiving the divisional voltages and the digital signal to select one of the divisional voltages. The selection circuit includes a plurality of first switch circuits that are selectively activated in response to the digital signal to select one of the divisional voltages, with each of the first switch circuits being provided with a logic switch function and having an ON resistance when activated, and at least an activated one of the first switch circuits further dividing the selected one of the divisional voltages with the ON resistance. The plurality of switch circuits includes at least one voltage dividing switch circuit used to further divide the selected one of the divisional voltages.Type: GrantFiled: August 6, 2007Date of Patent: July 12, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Hideto Fukuda, Shinya Udo, Masao Kumagai, Osamu Kudo
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Patent number: 7903071Abstract: A driver IC for a display that includes a first D/A converter with a 1st selection circuit that receives 1st image signals and supplies a selected positive divisional voltage to a 1st operational amplifier, which supplies a positive pixel voltage by amplifying the selected positive divisional voltage; a 2nd D/A converter with a 2nd selection circuit that receives 2nd image signals and supplies a selected negative divisional voltage to a 2nd operational amplifier, which supplies a negative pixel voltage by amplifying the selected negative divisional voltage; and a polarity switching switch with 1st and 2nd switches connecting the 1st and 2nd D/A converters respectively, the polarity switching switch being switched to supply each of output terminals corresponding to the 1st and 2nd image signals alternately with the positive and negative pixel voltages every horizontal scan period by activating/inactivating the 1st and 2nd switches in a complementary manner.Type: GrantFiled: August 6, 2007Date of Patent: March 8, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Hideto Fukuda, Shinya Udo, Masao Kumagai, Osamu Kudo
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Publication number: 20110044572Abstract: A sliding member is produced by forming hardening layers with two-layered structure on surface of a substrate metal with a Vickers hardness of not more than Hv300, such as aluminum or magnesium alloy for example, and then forming a DLC film having surface roughness defined as maximum height roughness Rz of 1 to 10 ?m further on the hardening layers. The above-described hardening layers are composed of a first hardening layer dispersed with heavy metal particles, preferably made of tungsten and/or tantalum in the substrate metal, and a second hardening layer formed under the first hardening layer.Type: ApplicationFiled: February 3, 2009Publication date: February 24, 2011Applicant: FUJIWPC CO., LTD.Inventors: Makoto Kano, Takahiro Horiuchi, Shinichi Takagi, Masao Kumagai, Eiji Shimodaira, Yoshio Miyasaka
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Patent number: 7838075Abstract: A method for strengthening a surface of a metal member. The method includes the following steps in the sequence set forth: (a) coating the surface of the metal member with a carbon-based film having a thickness of not smaller than 0.2 ?m; and (b) repeatedly applying a pressing force onto the surface of the film-coated metal member in a condition of maintaining a contact pressure of not lower than 2.5 GPa at the surface of the film-coated metal member.Type: GrantFiled: July 5, 2006Date of Patent: November 23, 2010Assignee: JATCO LtdInventors: Masao Kumagai, Yoshio Jimbo, Fumiya Yakabe
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Publication number: 20090250859Abstract: A device for manufacturing a connecting rod comprises a fixed stage secured onto a base, a movable stage so installed as to be move close to and apart from the fixed stage, and a set of backup cylinders displacing the overall movable stage along the axial direction of the connecting rod. The set of backup cylinders are substantially simultaneously biased to displace a cap part together with the movable stage until the fractured surface of the cap part of the connecting rod abuts on the fractured surface of the rod part of the connecting rod held on the fixed stage. Consequently, the removal and release of chips produced on the mating fractured surfaces can be promoted.Type: ApplicationFiled: November 8, 2006Publication date: October 8, 2009Inventors: Hideki Okumura, Tsuguo Koguchi, Masao Kumagai, Tomoyuki Shiga, Yuukou Hashimoto, Yoshiaki Yanata
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Patent number: 7580020Abstract: A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.Type: GrantFiled: July 17, 2006Date of Patent: August 25, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Shinya Udo, Masao Kumagai, Masatoshi Kokubun, Hidekazu Nishizawa, Takeo Shigihara
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Patent number: 7567873Abstract: An inspection method and an inspection apparatus that can easily measure a distribution of residual stress on a surface processed by shot peening, including a state of distribution in a depth direction of a material to be treated in a relatively short time without destroying the material to be treated. A coil provided in the inspection circuit is arranged on a surface processed by shot peening of the inspection target, an alternating current signal is input to the inspection circuit with changing a frequency so that frequency response characteristics of impedance of the inspection circuit is measured and acquired as inspection target data, and the inspection target data is compared to frequency response characteristics of impedance acquired from a sample of which a state of generation of residual stress is found.Type: GrantFiled: March 26, 2007Date of Patent: July 28, 2009Assignee: Fuji Manufacturing Co., Ltd.Inventors: Takashi Kojima, Masao Kumagai, Kiyoshi Hoshikawa, Shozo Ishibashi
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Publication number: 20080001609Abstract: To provide an inspection method and an inspection apparatus that can easily measure a distribution of residual stress on a surface processed by shot peening, including a state of distribution in a depth direction of a material to be treated in a relatively short time without destroying the material to be treated. A coil provided in the inspection circuit is arranged on a surface processed by shot peening of the inspection target, an alternating current signal is input to the inspection circuit with changing a frequency so that frequency response characteristics of impedance of the inspection circuit is measured and acquired as inspection target data, and the inspection target data is compared to frequency response characteristics of impedance acquired from a sample of which a state of generation of residual stress is found.Type: ApplicationFiled: March 26, 2007Publication date: January 3, 2008Inventors: Takashi Kojima, Masao Kumagai, Kiyoshi Hoshikawa, Shozo Ishibashi
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Publication number: 20070296678Abstract: A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.Type: ApplicationFiled: August 6, 2007Publication date: December 27, 2007Inventors: Hideto Fukuda, Shinya Udo, Masao Kumagai, Osamu Kudo
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Publication number: 20070296679Abstract: A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.Type: ApplicationFiled: August 6, 2007Publication date: December 27, 2007Inventors: Hideto Fukuda, Shinya Udo, Masao Kumagai, Osamu Kudo
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Patent number: 7268763Abstract: A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.Type: GrantFiled: November 5, 2003Date of Patent: September 11, 2007Assignee: Fujitsu LimitedInventors: Hideto Fukuda, Shinya Udo, Masao Kumagai, Osamu Kudo
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Patent number: 7215312Abstract: A display device includes a plurality of data drivers which are cascade-connected, and prevents variation of the duty ratio of a signal caused by accumulation of errors. In each of the plurality of data drivers: a first input circuit receives a first signal supplied from outside; a second input circuit receives a second signal supplied from outside, in response to the first signal received by the first input circuit; a signal processing circuit performs signal processing based on the second signal received by the second input circuit; a first output circuit inverts the first signal received by the first input circuit, and outputs the inverted first signal; and a second output circuit delays the second signal received by the second input circuit, by a predetermined amount, and outputs the delayed second signal.Type: GrantFiled: April 30, 2003Date of Patent: May 8, 2007Assignee: Fujitsu LimitedInventors: Masao Kumagai, Shinya Udo
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Patent number: 7180512Abstract: An integrated circuit includes a first signal-inversion switching circuit which receives a signal supplied from an exterior thereof as a first input signal, followed by outputting the first input signal after logic inversion thereof in response to a first state of a switching signal and outputting the first input signal without logic inversion in response to a second state of the switching signal, a signal processing circuit which performs signal processing based on the output of the first signal-inversion switching circuit, and a second signal-inversion switching circuit which receives the output of the first signal-inversion switching circuit passing through the signal processing circuit as a second input signal, followed by outputting the second input signal after logic inversion thereof in response to the second state of the switching signal and outputting the second input signal without logic inversion in response to the first state of the switching signal.Type: GrantFiled: January 3, 2003Date of Patent: February 20, 2007Assignee: Fujitsu LimitedInventors: Masao Kumagai, Hideto Fukuda, Shinya Udo
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Publication number: 20070009662Abstract: A method for strengthening a surface of a metal member. The method includes the following steps in the sequence set forth: (a) coating the surface of the metal member with a carbon-based film having a thickness of not smaller than 0.2 ?m; and (b) repeatedly applying a pressing force onto the surface of the film-coated metal member in a condition of maintaining a contact pressure of not lower than 2.5 GPa at the surface of the film-coated metal member.Type: ApplicationFiled: July 5, 2006Publication date: January 11, 2007Inventors: Masao Kumagai, Yoshio Jimbo, Fumiya Yakabe
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Publication number: 20060256052Abstract: A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.Type: ApplicationFiled: July 17, 2006Publication date: November 16, 2006Inventors: Shinya Udo, Masao Kumagai, Masatoshi Kokubun, Hidekazu Nishizawa, Takeo Shigihara
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Patent number: 7098878Abstract: A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.Type: GrantFiled: July 26, 2002Date of Patent: August 29, 2006Assignee: Fujitsu LimitedInventors: Shinya Udo, Masao Kumagai, Masatoshi Kokubun, Hidekazu Nishizawa, Takeo Shigihara
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Patent number: 7079104Abstract: A semiconductor device that operates with reduced power consumption having a clock transfer blocking circuit and an external data transfer blocking circuit that blocks a clock signal and a data signal from being transferred to a data output circuit when a data signal captured by a data capturing circuit is to be latched by a latch circuit. If however, the data signal captured is necessary for a later stage of the semiconductor device, then an internal data transfer blocking circuit blocks the data signal from being latched in the latch circuit, while the clock transfer blocking circuit and the external data transfer blocking circuit cause the captured clock signal and data signal to be output to the data output circuit.Type: GrantFiled: August 16, 2002Date of Patent: July 18, 2006Assignee: Fujitsu LimitedInventors: Masao Kumagai, Shinya Udo