Patents by Inventor Masao Kunimoto
Masao Kunimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6980553Abstract: A router apparatus 5 is provided with an ATM switch, an IP controller for performing routing control as a controller for layer 3, plural kinds of interfaces which are individually provided to plural transmission paths in which various communications are performed, and a cell multiplexing/demultiplexing unit, and manages the cell communications between respective parts on the basis of identification information. The input packet is subjected to IP processing in an interface to be converted to a cell in a common format, and the cell is serially multiplexed with a cell from another interface on a cell basis, and transmitted to the ATM switch at the cell multiplexing/demultiplexing unit. Each interface and each cell multiplexing/demultiplexing unit sets and switches the identification information for the header portion of the packet and the cell to be communicated by using a table in which the corresponding relationship of the identification information is registered.Type: GrantFiled: May 23, 2002Date of Patent: December 27, 2005Assignee: Hitachi, Ltd.Inventors: Kazuho Miki, Masahiro Takatori, Akihiko Takase, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Publication number: 20050008025Abstract: A router apparatus 5 is provided with an ATM switch, an IP controller for performing routing control as a controller for layer 3, plural kinds of interfaces which are individually provided to plural transmission paths in which various communications are performed, and a cell multiplexing/demultiplexing unit, and manages the cell communications between respective parts on the basis of identification information. The input packet is subjected to IP processing in an interface to be converted to a cell in a common format, and the cell is serially multiplexed with a cell from another interface on a cell basis, and transmitted to the ATM switch at the cell multiplexing/demultiplexing unit. Each interface and each cell multiplexing/demultiplexing unit sets and switches the identification information for the header portion of the packet and the cell to be communicated by using a table in which the corresponding relationship of the identification information is registered.Type: ApplicationFiled: July 20, 2004Publication date: January 13, 2005Inventors: Kazuho Miki, Masahiro Takatori, Akihiko Takase, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Publication number: 20020136244Abstract: A router apparatus 5 is provided with an ATM switch, an IP controller for performing routing control as a controller for layer 3, plural kinds of interfaces which are individually provided to plural transmission paths in which various communications are performed, and a cell multiplexing/demultiplexing unit, and manages the cell communications between respective parts on the basis of identification information. The input packet is subjected to IP processing in an interface to be converted to a cell in a common format, and the cell is serially multiplexed with a cell from another interface on a cell basis, and transmitted to the ATM switch at the cell multiplexing/demultiplexing unit. Each interface and each cell multiplexing/demultiplexing unit sets and switches the identification information for the header portion of the packet and the cell to be communicated by using a table in which the corresponding relationship of the identification information is registered.Type: ApplicationFiled: May 23, 2002Publication date: September 26, 2002Inventors: Kazuho Miki, Masahiro Takatori, Akihiko Takase, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Patent number: 6424662Abstract: A router apparatus 5 is provided with an ATM switch, an IP controller for performing routing control as a controller for layer 3, plural kinds of interfaces which are individually provided to plural transmission paths in which various communications are performed, and a cell multiplexing/demultiplexing unit, and manages the cell communications between respective parts on the basis of identification information. The input packet is subjected to IP processing in an interface to be converted to a cell in a common format, and the cell is serially multiplexed with a cell from another interface on a cell basis, and transmitted to the ATM switch at the cell multiplexing/demultiplexing unit. Each interface and each cell multiplexing/demultiplexing unit sets and switches the identification information for the header portion of the packet and the cell to be communicated by using a table in which the corresponding relationship of the identification information is registered.Type: GrantFiled: February 4, 2000Date of Patent: July 23, 2002Assignee: Hitachi, Ltd.Inventors: Kazuho Miki, Masahiro Takatori, Akihiko Takase, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Patent number: 6396808Abstract: A signal processing method for an ATM switching network formed by connecting a plurality of ATM switching networks in which header conversion tables of line interfaces can be rewritten by control cells, includes in response to occurrence of an abnormality in a call control processor of a ATM switching system A, informing an ATM switching system B of the occurrence of the abnormality, transferring call control information in the ATM switching system A to the ATM switching system B, rewriting header conversion tables included in a plurality of line interfaces of the ATM switching system A by using control cells generated by the ATM switching system A and thereby transferring signal channel cells arriving at the ATM switching system A after occurrence of the abnormality to the ATM switching system B, and rewriting header conversion tables included in a plurality of line interfaces of the ATM switching system A by using control cells generated by the ATM switching system B and thereby making a call control procesType: GrantFiled: March 6, 2000Date of Patent: May 28, 2002Assignee: Hitachi, Ltd.Inventors: Masao Kunimoto, Kenji Kawakita, Shinichi Iwaki, Satoshi Shimizu
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Patent number: 6385171Abstract: An LAN interface unit and an ATM switch unit cooperate to perform traffic control. A QoS unit monitors circumstances of an input buffer from a multiplexer of the ATM switch by means of a system controller and when an overflow of the input buffer is expected, the LAN interface unit of the multiplexer is instructed to perform traffic control. The LAN interface unit performs traffic control such as limitation of ATM cells inputted in the ATM switch.Type: GrantFiled: October 1, 1999Date of Patent: May 7, 2002Assignee: Hitachi, Ltd.Inventors: Akihiko Takase, Masahiro Takatori, Kazuho Miki, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Patent number: 6094433Abstract: A signal processing method for an ATM switching network formed by connecting a plurality of ATM switching networks in which header conversion tables of line interfaces can be rewritten by control cells, includes in response to occurrence of an abnormality in a call control processor of a ATM switching system A, informing an ATM switching system B of the occurrence of the abnormality, transferring call control information in the ATM switching system A to the ATM switching system B, rewriting header conversion tables included in a plurality of line interfaces of the ATM switching system A by using control cells generated by the ATM switching system A and thereby transferring signal channel cells arriving at the ATM switching system A after occurrence of the abnormality to the ATM switching system B, and rewriting header conversion tables included in a plurality of line interfaces of the ATM switching system A by using control cells generated by the ATM switching system B and thereby making a call control procesType: GrantFiled: December 6, 1995Date of Patent: July 25, 2000Assignee: Hitachi, Ltd.Inventors: Masao Kunimoto, Kenji Kawakita, Shinichi Iwaki, Satoshi Shimizu
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Patent number: 6046999Abstract: A router apparatus 5 is provided with an ATM switch, an IP controller for performing routing control as a controller for layer 3, plural kinds of interfaces which are individually provided to plural transmission paths in which various communications are performed, and a cell multiplexing/demultiplexing unit, and manages the cell communications between respective parts on the basis of identification information. The input packet is subjected to IP processing in an interface to be converted to a cell in a common format, and the cell is serially multiplexed with a cell from another interface on a cell basis, and transmitted to the ATM switch at the cell multiplexing/demultiplexing unit. Each interface and each cell multiplexing/demultiplexing unit sets and switches the identification information for the header portion of the packet and the cell to be communicated by using a table in which the corresponding relationship of the identification information is registered.Type: GrantFiled: February 13, 1998Date of Patent: April 4, 2000Assignee: Hitachi, Ltd.Inventors: Kazuho Miki, Masahiro Takatori, Akihiko Takase, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Patent number: 5963555Abstract: An LAN interface unit and an ATM switch unit cooperate to perform traffic control. A QoS unit monitors circumstances of an input buffer from a multiplexer of the ATM switch by means of a system controller and when an overflow of the input buffer is expected, the LAN interface unit of the multiplexer is instructed to perform traffic control. The LAN interface unit performs traffic control such as limitation of ATM cells inputted in the ATM switch.Type: GrantFiled: September 2, 1997Date of Patent: October 5, 1999Inventors: Akihiko Takase, Masahiro Takatori, Kazuho Miki, Masaru Murakami, Koji Wakayama, Tetsuro Yoshimoto, Masao Kunimoto
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Patent number: 5519690Abstract: A communication control apparatus connected between a transmission path and a processing unit which apparatus includes a table memory for storing the number of received frames which are in the state waiting for protocol processing in correspondence with connection identifiers, a first processor responsive to reception of a new frame from the aforementioned transmission path for making decision by referencing the memory table mentioned above as to whether or not the number of the received frames corresponding to the connection identifier of the newly received frame and waiting for the protocol processing has reached a threshold value for thereby abandoning the aforementioned newly received frame when that number has reached the threshold value and, if otherwise, placing the newly received frame in the state waiting for the protocol processing, and a second processor for executing a predetermined protocol processing on the received frame in the state waiting for the protocol processing.Type: GrantFiled: November 4, 1994Date of Patent: May 21, 1996Assignee: Hitachi, Ltd.Inventors: Tetsuya Suzuka, Masao Kunimoto, Shinichi Iwaki, Satoshi Shimizu
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Patent number: 5303236Abstract: A subscriber line signalling apparatus for use in an asynchronous mode communication system includes a switching circuit having a plurality of input terminals and a plurality of output terminals. The switching circuit selectively communicates fixed length information packets to an adaptation processing unit. The adaptation processing unit reassembles the fixed length packets to signalling frames, and transmits them to a frame processor.Type: GrantFiled: October 22, 1991Date of Patent: April 12, 1994Assignee: Hitachi, Ltd.Inventors: Masao Kunimoto, Jiro Kashio, Makoto Mori, Shinobu Gohara
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Patent number: 5214642Abstract: An adaptation processing apparatus for assembling received data units of a fixed length to provide variable length data units and transmitting the variable length data units to a plurality of variable length data unit processors while assembling variable length data units received from said plurality of the variable length data unit processors to provide fixed length data units for transmission thereof. An ATM switching system includes the adaptation processing apparatus, a signal processing unit including the plurality of variable length data unit processors mentioned above, and first-in first-out mechanisms for the variable length data units provided in the adaptation processing apparatus in association with every one of the plural variable length data unit processors.Type: GrantFiled: January 23, 1991Date of Patent: May 25, 1993Assignees: Hitachi, Ltd., Nippon Telegraph and Telephone CorporationInventors: Masao Kunimoto, Jiro Kashio, Kenji Kawakita, Shinobu Gohara, Shinichi Iwaki, Hiroyuki Ichikawa
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Patent number: 5208811Abstract: In a network system in which an interconnection is achieved between an LAN terminal connected to an LAN and an ISDN terminal linked with an ISDN via at least an LAN/ISDN inter-working unit coupling the LAN with the ISDN, the ISDN terminal develops a function to multiplex data link connections (communication paths) identified with respective data link connection identifiers (DLCIs) on ISDN channels. After conducting a call establishment to the ISDN terminal, the inter-working unit supplies the LAN terminal with an ISDN channel number and a DLCI designating an ISDN communication path. Thereafter, the LAN terminal sends an LAN frame having an OSI layer 2 header loaded with the communication path information to the inter-working unit. On receiving the LAN frame, the inter-working unit executes a format conversion to convert the LAN frame into an ISDN frame based on the ISDN communication path information.Type: GrantFiled: November 1, 1990Date of Patent: May 4, 1993Assignee: Hitachi, Ltd.Inventors: Jiro Kashio, Kenji Kawakita, Masao Kunimoto, Tetsuo Takemura, Takeshi Harakawa
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Patent number: 5175818Abstract: A communication system including a communication control unit connected through a communication line to a different system, a high-ranking processor for control of the communication control unit, and a common memory used for transfer of data between the high-ranking processor and the communication control unit. The communication control unit includes a direct memory access controller and a line controller interconnected via a transmission-only path and a reception-only path. The communication control unit autonomously generates an information frame and stores it in the common memory. The direct memory access controller then reads the information frame and transfers it to the line controller via the transmission-only path in order to transmit the information frame to the different system.Type: GrantFiled: February 21, 1989Date of Patent: December 29, 1992Assignee: Hitachi, Ltd.Inventors: Masao Kunimoto, Kenji Kawakita, Kenichi Kimura
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Patent number: 5164937Abstract: A method and system are provided for concentrating calls for a packet switching system in a hierarchical communication network. A plurality of terminals communicate with an associated plurality of packet concentrators that, in turn, communicate with switching equipment. The system and method comprise initiating a call at a call terminal to be communicated to the packet concentrator and identifying the call terminal by associating a line number communicating the terminal with the concentrator with a first logical channel number for communication from the packet concentrator to the switching equipment.Type: GrantFiled: July 12, 1990Date of Patent: November 17, 1992Assignee: Hitachi, Ltd.Inventors: Shirou Tanabe, Akihiko Takase, Masao Kunimoto, Yoshito Sakurai
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Patent number: 5101404Abstract: A subscriber line signalling apparatus for use in an asynchronous mode communication system includes a switching circuit having a plurality of input terminals and a plurality of output terminals. The switching circuit selectively communicates fixed length information packets to an adaptation processing unit. The adaptation processing unit reassembles the fixed length packets to signalling frames, and transmits them to a frame processor.Type: GrantFiled: August 21, 1989Date of Patent: March 31, 1992Assignee: Hitachi, Ltd.Inventors: Masao Kunimoto, Jiro Kashio, Makoto Mori, Shinobu Gohara