Abstract: A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.

Abstract: A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.

Abstract: A method of setting a plurality of different threshold voltage levels to a plurality of cell regions for a mask programmable semiconductor device by carrying out a second impurity first-code selective ion-implantation, into at least a first-selected one of said plurality of cell regions doped with a first impurity to have a first threshold voltage level so that the at least the first-selected one of said cell regions has a second threshold voltage level which is different from the first threshold voltage level, the second impurity of the first-code selective ion-implantation being heavier than said first impurity so as to suppress any excess thermal diffusion to avoid variations in threshold voltage level of the cell regions.

Abstract: In a conventional method, formation of an intermediate layer to serve as an insulating layer between a metal terminal on the surface of the device and a gate electrode of the device, along with heat treatment of the intermediate layer, is executed after formation of implanted diffusion layers to serve as bit lines of the device. In the method for manufacturing semiconductor memory devices according to the present invention, formation of the intermediate layer and heat treatment thereof are executed before formation of the implanted diffusion layers. The formation of the implanted diffusion layers is executed by introducing an impurity material into a memory cell region of the device with an energy enough to penetrate the intermediate layer. According to the method, heat diffusion of the impurity material due to the heat treatment step is prevented, and thus `Lmin`, i.e. the minimun channel length, can be set shorter and higher degree of integration of devices is made possible.

Abstract: A semiconductor read only memory device has a p-type contact region nested in a p-type drain region of a p-channel type field effect transistor and formed through a first ion-implantation of boron through a first opening of a photo-resist mask and a first contact hole of an inter-level insulating layer under a first acceleration energy too small to penetrate the inter-level insulating layer and a channel region of a memory transistor formed in a p-type well and formed through a second ion-implantation of phosphorous through a second opening of the photo-resist mask and the inter-level insulating layer under a second acceleration energy too large to stop the phosphorous in the p-type drain region so that the photo-resist mask is shared between the two ion-implantations.

Abstract: A fabrication method of a semiconductor integrated circuit device is provided. A patterned oxidation-resistant film such as silicon nitride film is formed on or over a semiconductor substrate. Using the patterned oxidation-resistant film as a mask, the substrate is then thermally oxidized so that a first oxide film for isolation is selectively formed to define active regions on the substrate. After the oxidation-resistant film is removed, the substrate is thermally oxidized so that a second oxide film is formed on the active regions, without adding any process step. Then, the substrate is etched until the second oxide film is entirely removed so that the surfaces of the active regions are exposed. During this process step, the first oxide film is partially removed. Subsequently, a patterned conductor film is formed on the first oxide film and then, it is removed from the first oxide.

Abstract: A fabrication method of a semiconductor memory device in which the punch-through phenomenon is difficult to occur in uncoded or unwritten memory cells. First impurity-doped regions for coding are formed in channel areas of selected ones of first MOS transistors in the memory cell area, using a patterned photoresist film as a mask, respectively. Second impurity-doped regions for threshold adjustment are formed in channel areas of unselected ones of the first transistors and second transistors in the peripheral circuit area, using a patterned photoresist film as a mask, respectively. During the process of forming the second impurity-doped regions, the dopant doped for threshold adjustment through the selected ones of the first transistors into the substrate forms third impurity-doped regions apart from the channel areas of the selected ones of the first transistors, respectively.