Abstract: A signal receiving circuit comprising a first P-channel MOSFET amplifier and a first N-channel MOSFET amplifier having gates supplied with positive signals from a pair of signal transmission lines; and a second P-channel MOSFET amplifier and a second N-channel MOSFET amplifier having gates supplied with negative signals from said pair of signal transmission lines; wherein a first output signal is formed by so adjusting the gains of the first P-channel MOSFET amplifier and of the second N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages, and a second output signal is formed by so adjusting the gains of the second P-channel MOSFET amplifier and of the first N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages.

Abstract: Write column selection MOSFETs of memory cells MC are coupled with, for example, the earth potential of the circuit. Write column selection signals supplied to these MOSFETs are formed selectively according to the column selection address signal and the write data. Thereby the write column selection MOSFETs of the memory cells MC function as a substantial write means. That is, the write column selection signal lines are used as the data lines at the same time.

Abstract: A differential type MOS transmission circuit includes a signal driving circuit and a signal receiving circuit to realize high speed transmission for a short distance transmission between different LSIs, etc. A pair of transmission lines between the signal driving circuit and the signal receiving circuit are driven by a pair of drivers in the signal driving circuit so as to take either one of three states, i.e. one state where both of the lines are in a precharged states and two states where either one of the lines is in a discharged state. A signal driving circuit includes signal generating circuits generating variations in control signals varying pulse-like in response to rise and fall of an input signal to thereby obtain the discharge state.

Abstract: One paired wiring traveling in parallel to a transmission path of a signal and a transmission path of reference voltage is used, and a terminal end resistor matched with the characteristic impedance is installed, and in a receiving circuit connected thereto, a differential input circuit with offset set to about 1/2 of the terminal end voltage is used, and an output circuit of open drain is used in a transmitting circuit. A high-speed information processing section using such a bus circuit and a low-speed information processing section using a conventional low-speed bus are mutually connected through an interface circuit to construct the system hierarchically.

Abstract: A signal transmission system provides stable, fast, long-range transmission. During transmission, a short-width pulse is synchronized with rising and falling edges of a transmission pulse signal. A ternary output signal in a differential shape is produced on the basis of the pulse, and an output signal is transmitted through series resistors via a pair of transmitting wirings. During reception, a reception terminal is provided with terminal resistors corresponding to a characteristic impedance of the transmitting wirings. A signal having passed through one of the transmitting wirings is detected with reference to a signal having passed through the other transmitting wiring. A signal having passed through the other transmitting wiring is detected with reference to the signal having passed through the one transmitting wiring. Additionally, the original pulse signal is restored and reproduced on the basis of the detected signals.

Abstract: A rate conversion circuit area (8) is provided between a spread gate area (4) which operates in synchronization with a clock signal CLK and a RAM core (7) (macro cell) operating in synchronization with a clock signal (ck) whose frequency is higher than that of the clock signal (CLK). With this arrangement, the single port core is made accessible as a dual port RAM by forming the clock signal (ck) whose frequency is multiplied an optional number of times that of the clock signal (CLK), receiving access data equivalent to a plurality of operating cycles in parallel from the spread gate area during a predetermined unit operating access cycle period in the spread gate area, and serially supplying these to the RAM core 7 during the plurality of operating cycle periods in synchronization with the clock signal (ck).

Abstract: A memory array of a static RAM or the like is divided in a word line extending direction to constitute a plurality of sub memory arrays SM0 to SM7, and array selecting signals for selecting the sub memory arrays and sub word line selecting signals for selecting sub word lines are combined to form word line selecting signals selectively. Main word lines M0000 to M0003 for transmitting those word line signals are arranged in parallel with the sub word lines SW000 to SW255. Sub word line drive circuits SWD000 to SWD255 are also coupled to the individual sub word lines for bringing the corresponding sub word lines selectively into selected states by combining at least 2 bits of the word line selecting signals.

Abstract: A signal transmission circuit in which a signal is converted into two complementary signals which are outputted from a signal transmission circuit via series resistors. The amplitude of each of the complimentary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of the signals which it inputs. The level shifted signals are amplified by a high-input impedance differential amplifying circuit.

Abstract: A signal transmission circuit in which a signal is converted into two complementary signals which are outputted from a signal transmission circuit via series resistors. The amplitude of each of the complimentary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of the signals which it inputs. The level shifted signals are amplified by a high-input impedance differential amplifying circuit.

Abstract: Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state.

Abstract: A semiconductor memory device has a sense amplifier which is constructed with a level shift circuit having an input which senses the change in a data line from an initial precharged level to a level near the vicinity of the supply voltage level which corresponds to data reading amounts from a memory cell during the reading mode of operation of the memory. The level shift circuit, in response to a memory cell reading signals, provides a level shifted outpout to the input terminal of a differential sense amplifier circuit, the level shifted output being in the vicinity of the operating point of the differential sense amplifier circuit. The level shift circuit includes a current amplifier having an output terminal that is formed with a series connecting node of a current amplifying transistor and a current source.

Abstract: Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state.

Abstract: A semiconductor memory device has a sense amplifier which is constructed with a level shift circuit having an input which senses the change in a data line from an initial precharged level to a level near the vicinity of the supply voltage level which corresponds to data reading amounts from a memory cell during the reading mode of operation of the memory. The level shift circuit, in response to a memory cell reading signals, provides a level shifted output to the input terminal of a differential sense amplifier circuit, the level shifted output being in the vicinity of the operating point of the differential sense amplifier circuit. The level shift circuit includes a current amplifier having an output terminal that is formed with a series connecting node of a current amplifying transistor and a current source.

Abstract: A variable displacement compressor comprises a housing forming a crank chamber, a shaft, expansible chambers including pistons, a swash plate connected to the shaft so as to be smoothly changeable in inclination against the shaft and driven to rotate, a wobble plate rotatable on the swash plate, a rotation preventing mechanism including a shoe member slidable in an axial direction, and a pressure control valve which is provided in a refrigerant passage from a suction port of the compressor to the expansible chamber to control the pressure of refrigerant to be sucked responsive to the suction pressure and both to the suction pressure and to the discharge pressure when the discharge pressure is high. The refrigerant passage has a sharply bent portion for separating lubrication oil from a refrigerant flowing therein and communicates with the crank chamber to discharge blow-by gas therefrom.

Abstract: A method of combining a plurality of parts and a structure of a plurality of parts combined by the method, wherein each of the plurality of parts are provided with connecting bores in opposed portions thereof, the plurality of parts are put together in a piled state and a connecting tube is inserted into the connecting bores. An expanding punch is provided for subsequently expanding the connecting tube thereby combining or connecting members to each other.

Abstract: A compressor of the rotary vane type including an annular space dormed inside a rotor for communicating vane slots formed in the rotor in communication with one another and for storing lubricant therein. As vanes each received in one of the vane slots move in radial sliding reciprocatory movement in the respective vane slots, the vanes are lubricated at their surfaces by the lubricant.

Abstract: A moving vane type compressor has a cylinder which is made of a sintered material having a density of 6.6 to 7.6 and a composition consisting essentially of 0.6 to 0.8% of carbon, 1 to 2% of copper and the balance substantially iron. The cylinder is encased by a hermetic casing therebetween a high pressure chamber into which a refrigerant compressed by the compressor is discharged. Lubricating oil separated from the discharged refrigerant within the high pressure chamber and the lubricating oil suspended in the form of a mist by the refrigerant attach to the outer peripheral surface of the wall of the cylinder made of the sintered material. The oil attaching to the outer peripheral surface of the cylinder is forced by the refrigerant pressure acting thereon into the pores of the sintered material such as to block these pores, thus preventing the compressed gas in the cylinder from leaking outside through the pores.

Abstract: A rotary compressor comprises a rotor, a cylinder having an inner surface slidably contacting the rotor at one or more portions thereof, side plates disposed on both sides of the cylinder for supporting a rotor driving shaft, and axial insert type discharge valves disposed inside the cylinder. The cylinder includes an inner cylinder having an inner surface slidably contacting the rotor, and an outer cylinder surrounding the whole of the outer periphery of the inner cylinder.

Abstract: The collectors of differential pair transistors having their emitters connected to each other are connected to a positive power source voltage via respective load resistors. The emitters are connected to a negative power source voltage via a current source transistor.The base bias voltage of the current source transistor is supplied from a bias circuit operating on the difference voltage between the positive power source voltage and the negative power source voltage.When the positive power source voltage drops, the base bias voltage of the current source transistor drops in response thereto. Hence, the value of a current flowing through the current source transistor decreases. Due to this decrease of the current, the voltage drop of the load resistors decreases, thereby off-setting a low level potential of the collector output signals of the differential pair transistors.Thus, the differential pair transistors are prevented from being driven into saturation.

Abstract: A level conversion circuit for converting a signal of a polarity to a signal of the opposite polarity has differential pair transistors, push-pull type output transistors adapted to receive the differential outputs of opposite phases from the differential pair transistors, a plurality of protective transistors for protecting the output transistors and a capacitance separation element connected between the common collector outputs of the plurality of protective transistors and the output of one of the differential pair transistors. The protective transistor prevents both of the differential outputs from simultaneously taking high level due to various operating conditions of the conversion circuit. Therefore, the deterioration or breakdown of the output transistors caused by the through current is avoided. The capacitance separation element also contributes to prevent the reduction of operation speed of the differential transistors caused by the collector capacitances of the plurality of protective transistors.