Abstract: A semiconductor device, includes a clock and data recovery unit to which a receive signal is inputted and which extracts, based on an operation clock signal, a clock signal and a data signal from the receive signal, a frequency error adjusting unit which generates a frequency error signal indicating a frequency error between the clock signal extracted from the receive signal and the operation clock signal, an operation clock generation unit which controls, based on the frequency error signal, a frequency of the operation clock signal, and a Spread Spectrum Clock Generator (SSCG) unit which varies the frequency of the operation clock signal by the SSCG unit based on the frequency error signal.

Abstract: A semiconductor device, includes a clock and data recovery unit to which a receive signal is inputted and which extracts, based on an operation clock signal, a clock signal and a data signal from the receive signal, a frequency error adjusting unit which generates a frequency error signal indicating a frequency error between the clock signal extracted from the receive signal and the operation clock signal, an operation clock generation unit which controls, based on the frequency error signal, a frequency of the operation clock signal, and a Spread Spectrum Clock Generator (SSCG) unit which varies the frequency of the operation clock signal by the SSCG unit based on the frequency error signal.

Abstract: A semiconductor device includes: a clock and data recovery unit to which a receive signal is inputted and which extracts, based on an operation clock signal, a clock signal and a data signal from the receive signal; a frequency error adjusting unit which generates a frequency error signal indicating a frequency error between the clock signal extracted from the receive signal and the operation clock signal; a frequency error signal storage unit which stores the frequency error signal; an operation clock generation unit which controls, based on the frequency error signal, a frequency of the operation clock signal; and an SSCG unit which, based on the value of the frequency error signal stored in the frequency error signal storage unit, varies the operation clock signal generated by the operation clock generation unit by spreading the spectrum of the operation clock signal.

Abstract: A controlling unit disposed in a PLL circuit controls a phase interpolator to gradually change a phase shift amount applied to a phase shift signal C_PS by a unit of basic delay amount ? at a timing predetermined in accordance with a modulation profile of an SSC. Further, the controlling unit controls a total phase shift amount applied to the phase shift signal C_PS output from the phase interpolator in one period of a feedback clock signal C_FB obtained by dividing frequency of the phase shift signal C_PS in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of C_FB is always equal to or less than the basic delay amount ?.

Abstract: A semiconductor device includes: a clock and data recovery unit to which a receive signal is inputted and which extracts, based on an operation clock signal, a clock signal and a data signal from the receive signal; a frequency error adjusting unit which generates a frequency error signal indicating a frequency error between the clock signal extracted from the receive signal and the operation clock signal; a frequency error signal storage unit which stores the frequency error signal; an operation clock generation unit which controls, based on the frequency error signal, a frequency of the operation clock signal; and an SSCG unit which, based on the value of the frequency error signal stored in the frequency error signal storage unit, varies the operation clock signal generated by the operation clock generation unit by spreading the spectrum of the operation clock signal.

Abstract: A controlling unit disposed in a PLL circuit controls a phase interpolator to gradually change a phase shift amount applied to a phase shift signal C_PS by a unit of basic delay amount ? at a timing predetermined in accordance with a modulation profile of an SSC. Further, the controlling unit controls a total phase shift amount applied to the phase shift signal C_PS output from the phase interpolator in one period of a feedback clock signal C_FB obtained by dividing frequency of the phase shift signal C_PS in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of C_FB is always equal to or less than the basic delay amount ?.

Abstract: A controlling unit disposed in a PLL circuit controls a phase interpolator to gradually change a phase shift amount applied to a phase shift signal C_PS by a unit of basic delay amount ? at a timing predetermined in accordance with a modulation profile of an SSC. Further, the controlling unit controls a total phase shift amount applied to the phase shift signal C_PS output from the phase interpolator in one period of a feedback clock signal C_FB obtained by dividing frequency of the phase shift signal C_PS in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of C_FB is always equal to or less than the basic delay amount ?.

Abstract: Disclosed is an SSC controller that exercises control to supply a control signal to a phase interpolator which receives an input clock signal and varies the phase of an output clock signal in accordance with the control signal, and to frequency-modulate the output clock signal. In an SSC controller, a counting operation control circuit outputs a counting operation control signal that controls count enable and disable. A p-counter receives a frequency-divided clock signal from a frequency divider and counts the signal when the counting operation control signal from the counting operation control circuit indicates count enable. Upon counting up to a predetermined first value, the counting operation control circuit generates a first output signal and sets its count value to zero. When the counting operation control signal indicates count disable, the p-counter stops counting.

Abstract: A semiconductor device includes a CDR (Clock Data Recovery) circuit and a frequency tracking control circuit. The CDR (Clock Data Recovery) circuit executes a clock data recovery on a serial data inputted synchronously with a spread spectrum clock. The frequency tracking control circuit controls a bandwidth of frequency which can be tracked by the CDR circuit.

Abstract: A controlling unit disposed in a PLL circuit controls a phase interpolator to gradually change a phase shift amount applied to a phase shift signal C_PS by a unit of basic delay amount ? at a timing predetermined in accordance with a modulation profile of an SSC. Further, the controlling unit controls a total phase shift amount applied to the phase shift signal C_PS output from the phase interpolator in one period of a feedback clock signal C_FB obtained by dividing frequency of the phase shift signal C_PS in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of C_FB is always equal to or less than the basic delay amount ?.

Abstract: A phase interpolator receives an input clock signal and varies the phase of an output clock signal in accordance with a phase control signal.

Abstract: A semiconductor device includes a CDR (Clock Data Recovery) circuit and a frequency tracking control circuit. The CDR (Clock Data Recovery) circuit executes a clock data recovery on a serial data inputted synchronously with a spread spectrum clock. The frequency tracking control circuit controls a bandwidth of frequency which can be tracked by the CDR circuit.

Abstract: A phase interpolator receives an input clock signal and varies the phase of an output clock signal in accordance with a phase control signal.

Abstract: Disclosed is an SSC controller that exercises control to supply a control signal to a phase interpolator which receives an input clock signal and varies the phase of an output clock signal in accordance with the control signal, and to frequency-modulate the output clock signal. In an SSC controller, a counting operation control circuit outputs a counting operation control signal that controls count enable and disable. A p-counter receives a frequency-divided clock signal from a frequency divider and counts the signal when the counting operation control signal from the counting operation control circuit indicates count enable. Upon counting up to a predetermined first value, the counting operation control circuit generates a first output signal and sets its count value to zero. When the counting operation control signal indicates count disable, the p-counter stops counting.

Abstract: A semiconductor integrated device includes a first insulating film 407 formed on any one of a conductive layer 406 and an interlayer insulating film 405, a first layer pad 408 which is in a two-layer pad and which is formed on the first insulating film 407, a third insulating film 413 deposited on both of the first insulating film 407 and the first layer pad 408 of the two-layer pad, a conductive plug 411 which is arranged to connect upper and lower pads of the two-layer pad and which is formed in the third insulating film 413, a second layer pad 401 which is in the two-layer pad and which is formed on the third insulating film 413, a second insulating film 409 which is formed on any one of the conductive layer 406 and the interlayer insulating film 405 and which has a film thickness greater than that of the first insulating film 407, and a single-layer pad 421 formed on the second insulating film 409.

Abstract: A semiconductor integrated device includes a first insulating film 407 formed on any one of a conductive layer 406 and an interlayer insulating film 405, a first layer pad 408 which is in a two-layer pad and which is formed on the first insulating film 407, a third insulating film 413 deposited on both of the first insulating film 407 and the first layer pad 408 of the two-layer pad, a conductive plug 411 which is arranged to connect upper and lower pads of the two-layer pad and which is formed in the third insulating film 413, a second layer pad 401 which is in the two-layer pad and which is formed on the third insulating film 413, a second insulating film 409 which is formed on any one of the conductive layer 406 and the interlayer insulating film 405 and which has a film thickness greater than that of the first insulating film 407, and a single-layer pad 421 formed on the second insulating film 409.