Abstract: A semiconductor integrated circuit device comprises a general purpose unit having a general purpose function and a specific unit for a specific use of the semiconductor integrated circuit device. In addition, the semiconductor integrated circuit device has structure in which a plurality of layers each having an integrated circuit formed therein are stacked in a three-dimensional manner. Specific unit layers are formed on the surface of the layer having the general purpose unit formed therein by different manufacturing processes.

Abstract: The device, for performing an orthogonal transformation of two dimensional discrete data array of n x n matrix at a high speed, includes a first block including storage elements for storing individual elements of a matrix for orthogonal transformation, a second block including storage elements for storing a data array therein, and a third block including a plurality of storage elements for storing a result of a multiplication therein, and n x n pointer registers each making a shifting operation in the row direction. When the pointer registers are reset, only diagonal elements thereof produce an activating signal.

Abstract: The present invention is directed to an integrated circuit having multilayer structure. In the present invention, dummy elements having no relation to the operation of an integrated circuit are formed on the upper surface of a substrate provided with the integrated circuit by the same material as that for the substrate, to thereby prevent the integrated circuit provided on the substrate from direct and correct observation. As the result, formation arrangement etc. of the integrated circuit cannot be easily analyzed, whereby interests of those contributing to technology development can be sufficiently protected.

Abstract: A method for producing a three-dimensional type semiconductor device comprises a first semiconductor integrated circuit layer comprising active regions, insulating layers, gate electrodes, and interconnection layers; an insulating layer formed thereon; and a second semiconductor integrated circuit layer comprising active regions, insulating layers, gate electrodes and interconnection layers. Active regions in the second layer are directly coupled to an interconnection layer, and active region and a gate electrode in the first layer, which are located immediately thereunder, by interlayer interconnections through a contact hole formed straight, so that a distance of each interlayer interconnection can be reduced.

Abstract: A bit length corresponding to a delay time of required data is preset in a bit length setting circuit (15). A write timing signal from an external control circuit (6) is applied to a write address decoder (3) and a read timing signal generating circuit (2). Input data is written into memory cells in a memory device (5) addressed by the write address decoder (3) operating in response to the write timing signal. On the other hand, a read timing signal generating circuit (2) generates a read timing signal delayed from the write timing signal by a delay time corresponding to a bit length signal in response to the bit length signal from the bit length setting circuit (15) and the write timing signal from outside. The read address decoder (4) sequentially addresses memory cells containing input data which have been written, reads written data and then outputs output data. Applications of the circuit include frame synchronization, variable delay and storage of picture data in a video communications system.

Abstract: This invention relates to a standard cell system large scale integrated circuit which comprises arraying a plurality of standard cells that are equally dimensioned in at least one direction and interconnection said standard cells so as to constitute a logic device, whereby the improvement is characterized in that wiring carrying a heavy load and being connected at many places on the surface of the chip is located within each of the standard cells, furthermore said wiring carrying a heavy load and being connected at many places on the surface of the chip is a clock line, and said clock line is located between a power line and a grounding conductor provided within each standard cell.

Abstract: A comparator bank of an A/D converter comprising a plurality of comparators arranged into rows in a folded-back shape and a supply voltage line and a ground line in parallel with each other and connected to the comparators to provide reference potentials thereto according to a distribution shape which rises and falls continuously along the rows of the comparators whereby the linearity of the A/D converter is effectively maintained. The nodes of the comparators do not intersect and are arranged to successively become further from reference points set at the terminals of the supply voltage and ground lines.

Abstract: A bidirectional elastic store circuit comprises an elastic store portion (1) having a node (A) for writing data and a node (B) for reading out data, an input terminal (8) and an output terminal (9) for data communication in a first direction, an input terminal (10) and an output terminal (11) for data communication in a second direction opposite to the first direction, a group of logical circuits (13) for selecting either the input terminals (8, 10) and a group of logical circuits (14) for selecting either the output terminals (9, 11). At the time of data communication in the first direction, a switching signal EN1/EN2 applied from an input terminal (12) becomes high, so that the input terminal (8) and the output terminal (9) are coupled to the elastic store portion (1) through the nodes (A) and (B), respectively.

Abstract: A detector for detecting the direction of incidence of ionized radiation comprises a laminated structure radiation detector which includes a plurality of planar structure detectors, each detector having a planar structure detector means constructed of a plurality of unit detectors arranged regularly on a plane and responsive to the ionized radiation. The planar detector further has position detector means which detects the position of the unit detector which has responded to ionized radiation. These planar structure detectors are arranged with a predetermined distance between them. The radiation detector further comprises direction of incidence calculating means for obtaining the direction of incidence of the ionized radiation from the outputs of the respective position detectors of the respective planar structure detectors.

Abstract: A submerged jet injection nozzle includes a nozzle exit disposed downstream of an orifice section and greater in diameter than the orifice section. The occurrence of cavitation due to a fluid injection is positively promoted so that the crushing effect of the cavitation is utilized fully and the decay in the energy of the injected fluid is reduced thereby increasing the work done by the submerged fluid injection.

Abstract: An arithmetic operation portion 3 comprises a plurality of multipliers 311 and 312 connected directly with a memory portion 1 so that multiplication processing can be performed in parallel. As a result, the processing capacity for multiplication and addition can be increased and the throughput rate of data can be improved.

Abstract: A capacitive element of a semiconductor integrated circuit comprising a first conductor provided in the input side and a second conductor provided in the output side further includes a third conductor to be connected with the first conductor. The front and back surfaces of the second conductor are entirely covered by the first and third conductors. Portions connecting the first and third conductors are arranged along the peripheral edge portions of the second conductor excepting a signal extracting portion.