Patents by Inventor Masao Nishida

Masao Nishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190202675
    Abstract: A hydraulic unit is provided with: a manifold which forms a hydraulic circuit; a tank which is joined to the manifold; and a hydraulic pump which suctions hydraulic fluid in the tank and supplies the hydraulic fluid to the manifold, wherein the base end portion of a suction strainer is fitted into the hydraulic pump, and the suction strainer has such a shape that the base end portion of the suction strainer is not separated from the hydraulic pump in a state where the leading end portion of the suction strainer is in contact with the tank and an opening through which the hydraulic fluid is introduced from the tank is provided at the leading end portion.
    Type: Application
    Filed: March 15, 2017
    Publication date: July 4, 2019
    Applicant: SHIMADZU CORPORATION
    Inventors: Masao OTO, Hideki HIGASHI, Hiroyuki NISHIDA
  • Patent number: 6854646
    Abstract: A transaction processing method is provided for a transaction management system which processes transactions using settlement cards. In the transaction processing method, a transaction process is executed based on individual control information that is input at each transaction and transaction information for the transaction. A judgment is made based on the transaction information whether or not the transaction satisfies at least one count-up condition indicating a predetermined range of transaction types. When the transaction meets the count-up condition, numerical information indicative of the number of transactions satisfying the count-up conditions is added. A determination is made whether or not a numerical value represented by the numerical information after the addition is within a range specified by extraction conditions.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: February 15, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Ieshima, Yuuji Ide, Takeshi Yokota, Ken Nozaki, Seiji Futatsugi, Masahiro Sakashita, Ryoji Satoh, Masao Nishida
  • Publication number: 20030120590
    Abstract: An electronic settlement system processes settlements that are conducted using credit cards through a communication line connecting a server of a credit card company to card-processing devices of member stores or terminals of customers. The electronic settlement system includes a device that provides personal information of customers to member stores based on the agreement by the customers to provide such personal information, and a device that provide the customers with preferred services either from the credit card company or the member stores in exchange for the personal information provided. Furthermore, the electronic settlement system may includes a device at the card company to receive fees for providing the member stores with the personal information of the customers. The electronic settlement system enables the customers to receive services, the member stores to utilize accurate personal information, and the card company to receive fees from the member stores.
    Type: Application
    Filed: July 15, 2002
    Publication date: June 26, 2003
    Applicant: HITACHI, LTD.
    Inventors: Takeshi Ieshima, Seiji Futatsugi, Masahiro Sakashita, Yuuji Ide, Ken Nozaki, Takeshi Yokota, Ryoji Satoh, Masao Nishida
  • Publication number: 20030066880
    Abstract: A transaction processing method is provided for a transaction management system which processes transactions using settlement cards. In the transaction processing method, a transaction process is executed based on individual control information that is input at each transaction and transaction information for the transaction. A judgment is made based on the transaction information whether or not the transaction satisfies at least one count-up condition indicating a predetermined range of transaction types. When the transaction meets the count-up condition, numerical information indicative of the number of transactions satisfying the count-up conditions is added. A determination is made whether or not a numerical value represented by the numerical information after the addition is within a range specified by extraction conditions.
    Type: Application
    Filed: July 11, 2002
    Publication date: April 10, 2003
    Applicant: HITACHI, LTD.
    Inventors: Takeshi Ieshima, Yuuji Ide, Takeshi Yokota, Ken Nozaki, Seiji Futatsugi, Masahiro Sakashita, Ryoji Satoh, Masao Nishida
  • Patent number: 6538537
    Abstract: A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: March 25, 2003
    Assignee: Sanyo Electric Co. Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Publication number: 20020113672
    Abstract: A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.
    Type: Application
    Filed: April 25, 2002
    Publication date: August 22, 2002
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Patent number: 6400240
    Abstract: A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: June 4, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Patent number: 6388540
    Abstract: In a distributed constant circuit, a first line is connected between a first node and a second node. The first node is grounded through a series connection between a first capacitor and a second line, and the second node is grounded through a series connection between a second capacitor and a third line. The parameters of the first, second and third lines and the first and second capacitors satisfy a predetermined relational expression such that characteristics equivalent to a &lgr;/4 line are obtained with respect to the frequency of a fundamental wave, and the second and third lines and the first and second capacitors respectively resonate with respect to an arbitrary frequency.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: May 14, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisanori Uda, Masao Nishida
  • Patent number: 6369655
    Abstract: A feedback circuit is connected between a drain electrode and a gate electrode of an FET. The feedback circuit is constituted by a series connection of a feedback amount adjusting resistor and an LC series resonance circuit. The LC series resonance circuit is constituted by a series connection of a capacitor and an inductor. The capacitance of the capacitor and the inductance of the inductor are set such that the LC series resonance circuit enters a short-circuited state with respect to an m-th harmonic by resonating at the frequency of the m-th harmonic, and the LC series resonance circuit enters an opened state with respect to a fundamental wave.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: April 9, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Patent number: 6281558
    Abstract: A high-voltage element (H)to which a high gate voltage is applied, and a low-voltage element (L) to which a low gate voltage is applied, are formed in a semiconductor substrate (1). Bird's beaks (8, 18) are formed in gate insulating films (7, 17) by thermal oxidation. Since a gate electrode (9) of the element (H) has a shorter gate length than a gate electrode (19) of the element (L), the ratio of the bird's beak in the gate insulating films (7, 17) is small in the element (L) and large in the element (H). Therefore, the element (H) has a high breakdown voltage and less aged deterioration, leading to long lifetime. The element (L) has a high current driving capability to produce high-speed operation. Thus, long lifetime, high operation speed and easy manufacturing steps are realized at the same time.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: August 28, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirokazu Sayama, Masao Nishida
  • Publication number: 20010008383
    Abstract: A feedback circuit is connected between a drain electrode and a gate electrode of an FET. The feedback circuit is constituted by a series connection of a feedback amount adjusting resistor and an LC series resonance circuit. The LC series resonance circuit is constituted by a series connection of a capacitor and an inductor. The capacitance of the capacitor and the inductance of the inductor are set such that the LC series resonance circuit enters a short-circuited state with respect to an m-th harmonic by resonating at the frequency of the m-th harmonic, and the LC series resonance circuit enters an opened state with respect to a fundamental wave.
    Type: Application
    Filed: January 17, 2001
    Publication date: July 19, 2001
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Publication number: 20010002116
    Abstract: A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.
    Type: Application
    Filed: December 18, 2000
    Publication date: May 31, 2001
    Applicant: Sanyo Electric Co, Ltd.
    Inventors: Masao Nishida, Tetsuro Sawai
  • Patent number: 6211754
    Abstract: A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: April 3, 2001
    Assignee: Sanyo Electric Co., Ltd,
    Inventors: Masao Nishida, Tetsuro Sawai
  • Patent number: 6140892
    Abstract: In a distributed constant circuit, a first line is connected between a first node and a second node. The first node is grounded through a series connection between a first capacitor and a second line, and the second node is grounded through a series connection between a second capacitor and a third line. The parameters of the first, second and third lines and the first and second capacitors satisfy a predetermined relational expression such that characteristics equivalent to a .lambda./4 line are obtained with respect to the frequency of a fundamental wave, and the second and third lines and the first and second capacitors respectively resonate with respect to an arbitrary frequency.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: October 31, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisanori Uda, Masao Nishida
  • Patent number: 6085145
    Abstract: An aircraft control system which assist in determining aircraft arrival orders and intervals, reduces controller's workloads, and ensures safe aircraft flight operation are provided.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: July 4, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yasuhiro Taka, Masao Nishida, Toshikazu Nakajima, Ryuji Otsuka
  • Patent number: 6064939
    Abstract: An individual guidance system for aircraft in an approach control area under automatic dependent surveillance which, by supplying the pilot with the required flight data automatically in units of micro air spaces, permits safe and accurate flight with little scope for human error, being an individual guidance system for aircraft in an approach control area under automatic dependent surveillance wherein the air-traffic control system divides the approach control area automatically into a group of micro air spaces, and establishes flight rules within the micro air spaces in order to guide aircraft by establishing no-fly air spaces.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: May 16, 2000
    Assignees: Oki Electric Industry Co., Ltd., Ship Research Institute, Toshiba Corporation
    Inventors: Masao Nishida, Yasuhiro Taka, Toshikazu Nakajima, Keiichiro Nakaue, Ryuji Otsuka, Kakuichi Shiomi, Yoichi Kusui
  • Patent number: 6052029
    Abstract: A capacitor is connected between the gate of an FET and an input node, and a resistor is connected between the input node and a ground terminal, thereby preventing the FET from oscillating in a low-frequency domain. A capacitor is connected between the drain of the FET and a ground terminal, or a line and a capacitor are connected in series between the drain of the FET and a ground terminal, thereby preventing the FET from oscillating in a high-frequency domain or at a specific frequency in the high-frequency domain.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: April 18, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hisanori Uda, Masao Nishida
  • Patent number: 6020831
    Abstract: A flight control system user interface apparatus and a control data display method thereof are provided to reduce a workload on a controller and to increase the safety of flight. A main-control terminal on a man-machine interface apparatus for use in a flight control system has an aircraft position display area 102, an aircraft order display area 102, a simple strip display area 104, an aircraft data display area 104, and a control pilot data link communication display area. These areas are arranged in such a way that they are controlled by one input unit.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: February 1, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masao Nishida, Yasuhiro Taka, Toshikazu Nakajima, Ryuji Otsuka
  • Patent number: 5614814
    Abstract: A negative voltage generating circuit includes an oscillating unit constructed of a ring oscillator for outputting a pulse signal with a high frequency and a polarity inverting unit in which the pulse signal is inputted to charge negative voltage. This negative voltage generating circuit is miniaturized and outputs a stable negative voltage. Further, the negative voltage to be outputted can be controlled by varying a resistance value through a control of an FET in a voltage controlling unit.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: March 25, 1997
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masao Nishida, Takayoshi Higashino, Yasoo Harada
  • Patent number: 5590412
    Abstract: A communication apparatus for use in a portable telephone is disclosed which has a transmit-receive common amplifier for amplifying a transmitted signal or received signal, and a mixer for frequency-mixing the transmitted signal or the received signal with a local oscillator output, wherein connection between the mixer and an input side of the amplifier and connection between the mixer and an output side of the amplifier are made by means of respective signal-path selector switches. During reception, a deep bias is applied to an FET of the transmit-receive common amplifier to reduce current consumption, and during transmission, a shallow bias is applied to the FET of the transmit-receive common amplifier for increased output.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: December 31, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Sawai, Hisanori Uda, Toshikazu Hirai, Toshikazu Imaoka, Yasoo Harada, Keiichi Honda, Masao Nishida