Patents by Inventor Masao Onose

Masao Onose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device
    Patent number: 7190593
    Abstract: A semiconductor integrated circuit device is provided in which (i) inspection pads are arranged along one side or two opposite sides of the semiconductor integrated circuit device for bonding pads arranged along the sides other than the side or the two opposite sides and (ii) the bonding pads are connected to their respective inspection pads by connection wires The inspection is carried out by applying probe needles to the pads (inspection pads and bonding pads) arranged only along one side or two opposite sides of the semiconductor integrated circuit device. The invention also provides a semiconductor integrated circuit package with leads on four sides includes a semiconductor integrated circuit device with bonding pads laid along one pair of opposite sides of the four sides, and a table for supporting the semiconductor integrated circuit device.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: March 13, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Kiyoshi Aiki, Kazunori Hikone, Hiroyuki Adachi, Masayoshi Okamoto, Masao Onose, Yuji Mizuno
  • Semiconductor integrated circuit device
    Publication number: 20020117729
    Abstract: A semiconductor integrated circuit device is provided in which (i) inspection pads are arranged along one side or two opposite sides of the semiconductor integrated circuit device for bonding pads arranged along the sides other than the side or the two opposite sides and (ii) the bonding pads are connected to their respective inspection pads by connection wires The inspection is carried out by applying probe needles to the pads (inspection pads and bonding pads) arranged only along one side or two opposite sides of the semiconductor integrated circuit device. The invention also provides a semiconductor integrated circuit package with leads on four sides includes a semiconductor integrated circuit device with bonding pads laid along one pair of opposite sides of the four sides, and a table for supporting the semiconductor integrated circuit device.
    Type: Application
    Filed: December 20, 2001
    Publication date: August 29, 2002
    Inventors: Kiyoshi Aiki, Kazunori Hikone, Hiroyuki Adachi, Masayoshi Okamoto, Masao Onose, Yuji Mizuno