Patents by Inventor Masao Orio

Masao Orio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080092010
    Abstract: An error correction code decoding device comprises a first memory having a memory space like a matrix, a first decoding unit writing a first information into the first memory along a first direction, a second decoding unit reading the first information from the first memory along a second direction and a plurality of turbo decoders included in the second decoding unit, and differentiating access timing to a same row or same column with each other.
    Type: Application
    Filed: October 11, 2007
    Publication date: April 17, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masao ORIO
  • Publication number: 20070180351
    Abstract: A decoding apparatus includes a first decoder and a second decoder as a decoding processor for performing iterative decoding on received data, a hard decision section for calculating hard decision results based on logarithmic likelihood ratios L1 and L2 from the first and second decoders, and a stop determination section performing stop determination on whether or not to stop the iterative decoding on the received data based on the result of the hard decision section. The decoding apparatus completes one-time iterative decoding by executing decoding process in each of the first and second decoders. The stop determination section executes stop determination at the timings of completion of the decoding process in the first decoder and completion of the decoding process in the second decoder.
    Type: Application
    Filed: January 12, 2007
    Publication date: August 2, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masao ORIO
  • Publication number: 20070162836
    Abstract: An arithmetic circuit includes a NOR circuit for outputting 1-bit inverted logical OR sf from all of a first bit group x(6) to x(10) containing 0 or more high-order bit of a path metric value composed of a plurality of bits, an inverter for inverting each bit of a second bit group x(2) to x(5) and outputting a third bit group rs(0) to rs(3), an AND circuit for outputting a fourth bit group ns(0) to ns(3) that contain results of calculating a logical AND of sf and rs(0) to rs(3), and a CF output section for outputting a correction factor CF based on ns(0) to ns(3).
    Type: Application
    Filed: December 7, 2006
    Publication date: July 12, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masao Orio
  • Publication number: 20070124657
    Abstract: A decoding apparatus includes a first decoder and a second decoder performing iterative decoding on each of a plurality of code blocks, each as a decoding unit, contained in a transport block, and a stop/end determination section determining whether or not to stop iterative decoding based on an output result from the second decoder. The stop/end determination section determines whether or not to stop the iterative decoding on each code block based on a determination result on whether error correction of iterative decoding in each code block is converted or not, and further determines whether or not to stop the iterative decoding of the transfer block based on the determination result in each code block. If it is determined that error correction of iterative decoding is not converted in one code block, the decoding process of the transport block containing the relevant code block is stopped.
    Type: Application
    Filed: November 1, 2006
    Publication date: May 31, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masao Orio
  • Publication number: 20060253769
    Abstract: A decoding device according to the one embodiment of the invention includes: a first decoder performing a first decoding based on first encoded data obtained by encoding unencoded data, and second soft-output data to generate first soft-output data; a second decoder performing a second decoding based on second encoded data obtained by interleaving the unencoded data and encoding the interleaved data, and the first soft-output data to generate the second soft-output data; and a hard decision part outputting decoded data through hard decision on the first soft-output data.
    Type: Application
    Filed: July 13, 2006
    Publication date: November 9, 2006
    Inventor: Masao Orio
  • Publication number: 20060085719
    Abstract: A decoding device according to the one embodiment of the invention includes: a first decoder performing a first decoding based on first encoded data obtained by encoding unencoded data, and second soft-output data to generate first soft-output data; a second decoder performing a second decoding based on second encoded data obtained by interleaving the unencoded data and encoding the interleaved data, and the first soft-output data to generate the second soft-output data; and a hard decision part outputting decoded data through hard decision on the first soft-output data.
    Type: Application
    Filed: October 13, 2005
    Publication date: April 20, 2006
    Inventor: Masao Orio
  • Publication number: 20040039769
    Abstract: A decoding method is provided which is capable of achieving decoding of error correcting codes in a simple configuration and in a short time. In the method of decoding error correcting codes to perform iterative decoding which consists of forward processing, backward processing, and extrinsic information value calculating processing, a second path metric value in a window boundary obtained at time of performing iterative decoding last time is used as an initial value of the second path metric value in a window boundary to be obtained at time of performing iterative decoding this time in the backward processing.
    Type: Application
    Filed: August 15, 2003
    Publication date: February 26, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Masao Orio