Patents by Inventor Masao Shimada
Masao Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150025859Abstract: A computer-implemented method for performing simulation includes establishing a mesh of a physical domain with nodes. The nodes represent a discretized physical quantity. The method accesses one or more different algorithms for evolving the nodes through sequential time steps. The method determines a unique combination of parameter values for each algorithm. In some examples, the parameter values can control dissipation, dispersion, and overshoot for each algorithm, as well as whether each algorithm is implicit or explicit. In some examples, the method can select one or more subsets of the nodes, and/or identify one or more time increments. The method can evolve the nodes in time, optionally using different time increments for different nodes in the mesh, and/or optionally using different algorithms for different nodes in the mesh. The method can optionally identify if an algorithm has failed to converge to a solution, and can switch to a different algorithm.Type: ApplicationFiled: June 25, 2014Publication date: January 22, 2015Inventors: Kumar K. Tamma, Masao Shimada, Siti Ujila Binti Masuri, Xiangmin Zhou
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Patent number: 8901605Abstract: There is provided a semiconductor wafer including a base wafer whose surface is entirely or partially a silicon crystal plane, an inhibitor positioned on the base wafer to inhibit crystal growth and having an opening that reaches the silicon crystal plane, a first crystal layer made of SixGe1-x (0?x<1) and positioned on the silicon crystal plane that is exposed in the opening, a second crystal layer positioned on the first crystal layer and made of a III-V Group compound semiconductor that has a band gap width larger than a band gap width of the first crystal layer, and a pair of metal layers positioned on the inhibitor and the second crystal layer. The pair of the metal layers are each in contact with the first crystal layer and the second crystal layer.Type: GrantFiled: September 5, 2013Date of Patent: December 2, 2014Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Tomoyuki Takada, Sadanori Yamanaka, Masao Shimada, Masahiko Hata, Taro Itatani, Hiroyuki Ishii, Eiji Kume
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Publication number: 20140008698Abstract: There is provided a semiconductor wafer including a base wafer whose surface is entirely or partially a silicon crystal plane, an inhibitor positioned on the base wafer to inhibit crystal growth and having an opening that reaches the silicon crystal plane, a first crystal layer made of SixGe1-x (0?x<1) and positioned on the silicon crystal plane that is exposed in the opening, a second crystal layer positioned on the first crystal layer and made of a III-V Group compound semiconductor that has a band gap width larger than a band gap width of the first crystal layer, and a pair of metal layers positioned on the inhibitor and the second crystal layer. The pair of the metal layers are each in contact with the first crystal layer and the second crystal layer.Type: ApplicationFiled: September 5, 2013Publication date: January 9, 2014Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Tomoyuki TAKADA, Sadanori YAMANAKA, Masao SHIMADA, Masahiko HATA, Taro ITATANI, Hiroyuki ISHII, Eiji KUME
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Patent number: 7724679Abstract: A network information detection apparatus includes a packet monitoring section and a subnet mask detection section. The packet monitoring section monitors packets on LAN connecting a plurality of network devices. Based on an IP address included in at least one monitored packet, the subnet mask detection section detects a subnet mask of a network device having the monitored IP address. When a destination MAC address and a destination IP address included in the monitored packet do not indicate the same network device, a router of the LAN can be detected by detecting an IP address corresponding to the destination MAC address.Type: GrantFiled: July 1, 2003Date of Patent: May 25, 2010Assignee: NEC CorporationInventor: Masao Shimada
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Patent number: 7707332Abstract: An I/O-request processing system which is capable of reducing the maximum value of the time required until the I/O request of each external device is registered. An I/O-request receiving section (501) receives an I/O request issued from an external device (600). A process-information storage section (510) stores an I/O-request delay time (512) for each external device (600). A priority-process judgment section (520) registers the I/O request having a maximum I/O-request delay time (512) among the I/O requests which have been registered into an I/O-request cue (540).Type: GrantFiled: October 12, 2006Date of Patent: April 27, 2010Assignee: NEC CorporationInventor: Masao Shimada
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Publication number: 20100023989Abstract: When a relay device receives a content transmitted from a first communication device toward a second communication device, the relay device performs relay processing of transmitting the content toward the second communication device. When, during the relay processing, the relay device receives a transmission request for the content, which has been transmitted from a third communication device toward the first communication device, the relay device performs transmission processing of transmitting a first section of the content, which has not been transmitted in the relay processing at a time of reception of the transmission request, from the relay device toward the third communication device in synchronization with transmission of the first section performed in the relay processing.Type: ApplicationFiled: July 22, 2009Publication date: January 28, 2010Inventor: MASAO SHIMADA
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Patent number: 7636791Abstract: Search IP addresses are detected from among a preset number of selected IP addresses available on the network, and DNS query message and ICMP echo request message are transmitted at a time to the detected search IP addresses. DNS server and router IP addresses are detected from response messages in response to the DNS query message and the ICMP echo request message.Type: GrantFiled: March 18, 2004Date of Patent: December 22, 2009Assignee: NEC CorporationInventor: Masao Shimada
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Publication number: 20090083744Abstract: An information writing/reading system includes a thread scheduler unit configured to control a sequence of execution for a plurality of threads, a thread execution unit, a device driver unit configured, a disk mechanism, an end time estimation unit configured to estimate an end time of execution of an issued write command, and a command management unit, wherein the thread scheduler unit is configured to temporarily suspend execution of at least one read thread of the plurality of threads if the command management unit determines that an estimated end time of execution of the issued write command is greater than an end time designated by the issued write command.Type: ApplicationFiled: September 25, 2008Publication date: March 26, 2009Applicant: NEC CorporationInventor: MASAO SHIMADA
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Publication number: 20090049217Abstract: An I/O-request processing system which is capable of reducing the maximum value of the time required until the I/O request of each external device is registered. An I/O-request receiving section (501) receives an I/O request issued from an external device (600). A process-information storage section (510) stores an I/O-request delay time (512) for each external device (600). A priority-process judgment section (520) registers the I/O request having a maximum 1o I/O-request delay time (512) among the I/O requests which have been registered into an I/O-request cue (540).Type: ApplicationFiled: October 12, 2006Publication date: February 19, 2009Applicant: NEC CorporationInventor: Masao Shimada
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Publication number: 20080205220Abstract: A recording apparatus includes: a performance determining unit measuring recording speeds on each of unit data sizes recorded by plural kinds of access pattern to a storing device and generating performance information indicating results of the measurement; a recording request receiving unit receiving a recording request including data to be recorded on the storing device and information of size of said data; and a recording control unit selecting an access pattern corresponding to higher recording speed as well as the information of data size included in the recording request from the performance information and instructing the storing device to perform a recording process using the selected access pattern.Type: ApplicationFiled: February 21, 2008Publication date: August 28, 2008Inventor: MASAO SHIMADA
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Publication number: 20040184458Abstract: Search IP addresses are detected from among a preset number of selected IP addresses available on the network, and DNS query message and ICMP echo request message are transmitted at a time to the detected search IP addresses DNS server and router IP addresses are detected from response messages in response to the DNS query message and the ICMP echo request message.Type: ApplicationFiled: March 18, 2004Publication date: September 23, 2004Applicant: NEC CORPORATIONInventor: Masao Shimada
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Publication number: 20040017814Abstract: ABSTRACT A network information detection apparatus includes a packet monitoring section and a subnet mask detection section. The packet monitoring section monitors packets on LAN connecting a plurality of network devices. Based on an IP address included in at least one monitored packet, the subnet mask detection section detects a subnet mask of a network device having the monitored IP address. When a destination MAC address and a destination IP address included in the monitored packet do not indicate the same network device, a router of the LAN can be detected by detecting an IP address corresponding to the destination MAC address.Type: ApplicationFiled: July 1, 2003Publication date: January 29, 2004Applicant: NEC CORPORATIONInventor: Masao Shimada
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Patent number: 6432743Abstract: A surface of a semiconductor wafer having a plurality of semiconductor elements thereon is laminated on a first wafer holding substrate. Subsequently, the whole rear surface of the semiconductor wafer is coated with a first conductive layer. Then a second conductive layer is selectively formed thereon. Then, a rear surface side glass substrate is laminated on the first and second conductive layer. Subsequently, the first wafer holding substrate is peeled off. Subsequently, the semiconductor wafer is selectively etched so as to be separated into semiconductor elements. Then, the first conductive layer is connected to a ground potential to measure electrical characteristics of the semiconductor elements and sort the semiconductor elements into non-defectives and defectives. Then, the first conductive layer is selectively etched so as to be separated into chips and thus semiconductor pellets are formed. Finally, the second wafer holding substrate is peeled off.Type: GrantFiled: April 23, 2001Date of Patent: August 13, 2002Assignee: NEC CorporationInventor: Masao Shimada
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Publication number: 20010034081Abstract: A surface of a semiconductor wafer having a plurality of semiconductor elements thereon is laminated on a first wafer holding substrate. Subsequently, the whole rear surface of the semiconductor wafer is coated with a first conductive layer. Then a second conductive layer is selectively formed thereon. Then, a rear surface side glass substrate is laminated on the first and second conductive layer. Subsequently, the first wafer holding substrate is peeled off. Subsequently, the semiconductor wafer is selectively etched so as to be separated into semiconductor elements. Then, the first conductive layer is connected to a ground potential to measure electrical characteristics of the semiconductor elements and sort the semiconductor elements into non-defectives and defectives. Then, the first conductive layer is selectively etched so as to be separated into chips and thus semiconductor pellets are formed. Finally, the second wafer holding substrate is peeled off.Type: ApplicationFiled: April 23, 2001Publication date: October 25, 2001Applicant: NEC CorporationInventor: Masao Shimada
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Patent number: 6166641Abstract: A termite sensor and intrusion detection system for detecting the intrusion of termites into wooden buildings. Conductive particles fill a container which termites can eat. A pair of electrodes are disposed opposite each other inside the container. A pair of terminals are connected to the electrodes and extend outside the container. Termites are detected by a change of conductivity between the electrodes, when termites are detected a warning device generates a warning signal.Type: GrantFiled: November 29, 1999Date of Patent: December 26, 2000Assignees: Toshiba Chemical Corporation, Ikari CorporationInventors: Toshihiko Oguchi, Fumio Nakaya, Masao Shimada
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Patent number: 6140506Abstract: The present invention produces novel cis-oxazolidinone compound which is racemic form or optically active form, of a formula (1) ##STR1## wherein R represents C.sub.1 -C.sub.6 alkyl group, C.sub.2 -C.sub.6 alkenyl group, C.sub.1 -C.sub.6 alkoxyl group, C.sub.1 -C.sub.6 alkylamino group, aryl group or halogen atom, and oxazolidinone ring is at cis-configuration, comprising reacting cis-1,2-indene epoxide of a formula (3) ##STR2## form, with sulfonyl isocyanate compound of a formula (4) ##STR3## in the presence of metal halide catalyst. Further, cis-1-amino-2-indanol is produced by hydrolyzing the oxazolidinone compound. The latter compound is useful as an intermediate of HIV-drug.Type: GrantFiled: December 30, 1998Date of Patent: October 31, 2000Assignee: Nissan Chemical Industries, Ltd.Inventors: Akio Baba, Kenji Suzuki, Yoshinobu Yanagawa, Yoko Ohkuni, Takashi Oda, Masao Shimada, Masami Kozawa
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Patent number: 5840561Abstract: A novel phytase is disclosed. The phytase consists essentially of a single type of subunits, and can hydrolyze a phytate to myo-inositol. A gene encoding the phytase, which is originated from Schwanniomyces occidentalis is also disclosed.Type: GrantFiled: November 24, 1997Date of Patent: November 24, 1998Assignee: Mitsui Chemicals, Inc.Inventors: Daisuke Mochizuki, Junko Tokudo, Tadashi Suzuki, Masao Shimada, Shin-ichirou Tawaki
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Patent number: 5830732Abstract: A novel phytase is disclosed. The phytase consists essentially of a single type of subunits, and can hydrolyze a phytate to myo-inositol. A gene encoding the phytase, which is originated from Schwanniomyces occidentalis is also disclosed.Type: GrantFiled: July 3, 1995Date of Patent: November 3, 1998Assignee: Mitsui Toatsu Chemicals, Inc.Inventors: Daisuke Mochizuki, Junko Tokuda, Tadashi Suzuki, Masao Shimada, Shin-ichirou Tawaki
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Patent number: 5443973Abstract: A culture liquid of microorganisms having an ability of producing .alpha.-hydroxyisobutylamide from acetone cyanhydrin or the cultivated cells of the microorganisms or the processed cells of them is/are reacted to acetone cyanhydrin in an aqueous medium to produce .alpha.-hydroxyisobutylamide. The amide is reacted with water and/or an aliphatic alcohol in the presence of a solid acid catalyst at a temperature of 150.degree. C. or higher in a gaseous phase or a gaseous-liquid mixed phase to produce an .alpha.,.beta.-unsaturated carboxylate or an aliphatic alcohol or an .alpha.,.beta.-unsaturated carboxylic acid.Type: GrantFiled: August 19, 1992Date of Patent: August 22, 1995Assignee: Mitsui Toatsu Chemicals, Inc.Inventors: Kenichi Soshiwata, Masao Shimada, Akira Hatamori
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Patent number: 5038294Abstract: Generating apparatus and method by which all steps of the procedure for generating a configuration diagram of connection between a plurality of units constituting a system can be automated. The automatic connection configuration diagram generating system comprises a first memory for storing data indicative of the units by which the system is constituted, a second memory for storing data indicative of a layout according to which the units of the system are laid, a knowledge base for incorporating a set of rules indicative of connection specifications for all of the units of the system, a selector for selecting connection specification rules for desired units from the rule set stored in the knowledge base, a controller for determining a connection structure on the basis of the selected rules and the data stored in the first and second memories, and a third memory for storing the connection structure determined by the controller.Type: GrantFiled: November 16, 1988Date of Patent: August 6, 1991Assignee: Hitachi, Ltd.Inventors: Hiroshi Arakawa, Masao Shimada, Isao Nakada