Patents by Inventor Masao Shindo

Masao Shindo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210320204
    Abstract: The semiconductor device includes: a gate electrode on a semiconductor substrate via a gate insulating film; an offset drain layer in the semiconductor substrate on one side of the gate electrode; a drain layer on the offset drain layer; and a source layer in the semiconductor substrate on another side of the gate electrode. The semiconductor device further includes: a protective film covering the semiconductor substrate; a field plate on the protective film, and having a portion above the offset drain layer; and a field plug connected to the field plate and in the protective film and above the offset drain layer, in such a manner as to avoid reaching the offset drain layer.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Applicants: TOWER PARTNERS SEMICONDUCTOR CO., LTD., TOWER SEMICONDUCTOR LTD.
    Inventors: Masao SHINDO, Takayuki YAMADA, Yoshinobu MOCHO, Toshihiko ICHIKAWA, Noriyuki INUISHI, Hideo ICHIMURA, Norio KOIKE, Sharon LEVIN, Hongning YANG, David MISTELE, Daniel SHERMAN
  • Patent number: 6815301
    Abstract: A method for fabricating a bipolar transistor includes: a first step of implanting, along the normal direction of the principle surface of a first-conductive-type semiconductor single crystalline substrates ions of a second-conductive-type first impurity into the semiconductor single crystalline substrate to form a second-conductive-type collector layer; a second step of implanting, along the direction tilted from the normal direction, ions of a second-conductive-type second impurity into the semiconductor single crystalline substrate at a higher injection energy than that in the ion implantation of the first step to form a buried collector layer in a lower portion of the collector layer; and a third step of forming each of a first-conductive-type base layer and a second-conductive-type emitter layer in a predetermined region of a surface portion of the collector layer.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: November 9, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masao Shindo
  • Publication number: 20040192005
    Abstract: A method for fabricating a bipolar transistor includes: a first step of implanting, along the normal direction of the principle surface of a first-conductive-type semiconductor single crystalline substrate, ions of a second-conductive-type first impurity into the semiconductor single crystalline substrate to form a second-conductive-type collector layer; a second step of implanting, along the direction tilted from the normal direction, ions of a second-conductive-type second impurity into the semiconductor single crystalline substrate at a higher injection energy than that in the ion implantation of the first step to form a buried collector layer in a lower portion of the collector layer; and a third step of forming each of a first-conductive-type base layer and a second-conductive-type emitter layer in a predetermined region of a surface portion of the collector layer.
    Type: Application
    Filed: February 20, 2004
    Publication date: September 30, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Masao Shindo
  • Patent number: 5451911
    Abstract: A timing generator contains an oscillator section (10) formed with a plural number of stages (S.sub.1 -S.sub.N) for respectively producing a like number of stage signals (V.sub.S1 -V.sub.SN) that sequentially change signal values at a basic oscillator frequency (f.sub.O). The oscillator section is typically implemented as a ring oscillator. In response to the stage signals, a timing-signal generating section (14) generates one or more timing signals (V.sub.T1 -V.sub.TM), each having at least two transitions corresponding to transitions of two or more of the stage signals. A control section (12), preferably arranged in a phase-locked loop, causes the oscillator frequency and a reference frequency (f.sub.R) to have a substantially fixed relationship.
    Type: Grant
    Filed: April 7, 1994
    Date of Patent: September 19, 1995
    Assignee: Media Vision, Inc.
    Inventors: Bryan J. Colvin, Masao Shindo