Patents by Inventor Masao Shinozaki
Masao Shinozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8611166Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.Type: GrantFiled: August 13, 2012Date of Patent: December 17, 2013Assignee: Renesas Electronics CorporationInventor: Masao Shinozaki
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Patent number: 8351283Abstract: The present invention is directed to realize high-speed operation and low latency of a semiconductor storage device employing the QDR method. A memory cell array, a first buffer, a second buffer, a first circuit, a second circuit, a first DLL circuit, and a second DLL circuit are provided. The first DLL circuit generates a first internal clock signal so as to reduce a phase difference between a first clock signal fetched via the first buffer and the first internal clock signal transmitted to the first circuit. The second DLL circuit generates the second internal clock signal so as to reduce a phase difference between the second clock signal fetched via the second buffer and the second internal clock signal transmitted to the second circuit. With the configuration, input setup and hold time can be shortened, and the frequency of the clock signal can be further increased.Type: GrantFiled: June 13, 2010Date of Patent: January 8, 2013Assignee: Renesas Electronics CorporationInventors: Masao Shinozaki, Hajime Sato
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Publication number: 20120320664Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.Type: ApplicationFiled: August 13, 2012Publication date: December 20, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Masao SHINOZAKI
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Patent number: 8279696Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.Type: GrantFiled: May 6, 2011Date of Patent: October 2, 2012Assignee: Renesas Electronics CorporationInventor: Masao Shinozaki
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Patent number: 8130581Abstract: The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.Type: GrantFiled: October 26, 2010Date of Patent: March 6, 2012Assignee: Renesas Electronics CorporationInventors: Hajime Sato, Masao Shinozaki
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Publication number: 20110211385Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.Type: ApplicationFiled: May 6, 2011Publication date: September 1, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Masao SHINOZAKI
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Patent number: 7982314Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: July 21, 2010Date of Patent: July 19, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 7961500Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.Type: GrantFiled: April 30, 2009Date of Patent: June 14, 2011Assignee: Renesas Electronics CorporationInventor: Masao Shinozaki
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Patent number: 7903490Abstract: The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.Type: GrantFiled: September 16, 2008Date of Patent: March 8, 2011Assignee: Renesas Electronics CorporationInventors: Hajime Sato, Masao Shinozaki
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Publication number: 20110044095Abstract: The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.Type: ApplicationFiled: October 26, 2010Publication date: February 24, 2011Inventors: Hajime Sato, Masao Shinozaki
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Publication number: 20100322022Abstract: The present invention is directed to realize high-speed operation and low latency of a semiconductor storage device employing the QDR method. A memory cell array, a first buffer, a second buffer, a first circuit, a second circuit, a first DLL circuit, and a second DLL circuit are provided. The first DLL circuit generates a first internal clock signal so as to reduce a phase difference between a first clock signal fetched via the first buffer and the first internal clock signal transmitted to the first circuit. The second DLL circuit generates the second internal clock signal so as to reduce a phase difference between the second clock signal fetched via the second buffer and the second internal clock signal transmitted to the second circuit. With the configuration, input setup and hold time can be shortened, and the frequency of the clock signal can be further increased.Type: ApplicationFiled: June 13, 2010Publication date: December 23, 2010Inventors: Masao Shinozaki, Hajime Sato
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Publication number: 20100308458Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: ApplicationFiled: July 21, 2010Publication date: December 9, 2010Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 7808107Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: May 8, 2009Date of Patent: October 5, 2010Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 7685455Abstract: A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.Type: GrantFiled: November 7, 2007Date of Patent: March 23, 2010Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroaki Nambu, Masao Shinozaki, Kazuo Kanetani, Hideto Kazama
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Patent number: 7656733Abstract: This invention provides a semiconductor memory device with enhanced speed performance or enabling timing adjustment reflected in characteristic variation of memory cells, adapted to suppress an increase in the number of circuit elements. A write dummy bit section comprises a first dummy line and a second dummy line corresponding to complementary bit lines and a plurality of first dummy cells formed to be similar in shape to static memory cells, wherein a write current path is coupled between the first dummy line and the second dummy line. In the write dummy bit section, one voltage level is input to the first dummy line through driver MOSFETs in relation to write signal inputs to the static memory cells and a signal change in the second dummy line precharged at the other voltage level is sensed and output. A timing control circuit deselects a word line selected by an output signal from the write dummy bit section.Type: GrantFiled: March 31, 2008Date of Patent: February 2, 2010Assignee: Renesas Technology Corp.Inventors: Masao Shinozaki, Hajime Sato
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Publication number: 20090323400Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.Type: ApplicationFiled: April 30, 2009Publication date: December 31, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventor: Masao SHINOZAKI
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Publication number: 20090219069Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: ApplicationFiled: May 8, 2009Publication date: September 3, 2009Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 7547971Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: August 12, 2005Date of Patent: June 16, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Publication number: 20090027986Abstract: The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.Type: ApplicationFiled: September 16, 2008Publication date: January 29, 2009Inventors: Hajime Sato, Masao Shinozaki
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Publication number: 20080279033Abstract: A semiconductor integrated circuit device provided with a memory circuit having a word line selection circuit with reduced leakage current is provided. The memory circuit includes: second word lines with which memory cells are connected; multiple bit lines that are extended in a direction orthogonal thereto and electrically connected with memory cells corresponding to selected second word lines of a plurality of the second word lines; and word drivers, constructed of CMOS inverter circuits, that select or deselect the second word lines. The sources of p-channel MOSFETs that constitute a plurality of word drivers including second word lines corresponding to selected bit lines are supplied with a voltage at a level at which second word lines are selected. The sources of the p-channel MOSFETs of the other word drivers are supplied with a voltage corresponding to a level at which second word lines are deselected.Type: ApplicationFiled: July 15, 2008Publication date: November 13, 2008Inventors: Masao Shinozaki, Daisuke Shimadu